4710 Syscon
From embeddedTS Manuals
The registers listed below are all 16 bit registers and must be accessed with 16 bit reads and writes. This register block appears at base address 0x80004000. For example, to identify the model:
devmem 0x80004000 16
This will return 0x4710, 0x4712, 0x4720, or 0x4740 depending on the model.
Many of the syscon options can be manipulated using tshwctl.
Usage: tshwctl [OPTION] ... Technologic Systems TS-471x / TS-77XX FPGA manipulation. General options: -g, --getmac Display ethernet MAC address -s, --setmac=MAC Set ethernet MAC address -R, --reboot Reboot the board -t, --getrtc Get system time from RTC time/date -S, --setrtc Set RTC time/date from system time -F, --rtcinfo Print RTC temperature, poweron/off time, etc -v, --nvram Get/Set RTC NVRAM -i, --info Display board FPGA info -e, --greenledon Turn green LED on -b, --greenledoff Turn green LED off -c, --redledon Turn red LED on -d, --redledoff Turn red LED off -D, --setdio=<pin> Sets DDR and asserts a specified pin -O, --clrdio=<pin> Sets DDR and deasserts a specified pin -G, --getdio=<pin> Sets DDR and gets DIO pin input value -x, --random Get 16-bit hardware random number -W, --watchdog Daemonize and set up /dev/watchdog -n, --setrng Seed the kernel random number generator -X, --resetswitchon Enable reset switch -Y, --resetswitchoff Disable reset switch -l, --loadfpga=FILE Load FPGA bitstream from FILE -q, --cputemp Display the CPU die temperature -U, --removejp=JP Remove soft jumper numbered JP (1-8) -J, --setjp=JP Set soft jumper numbered JP (1-8) -k, --txenon=XUART(s) Enables the TX Enable for an XUART -K, --txenoff=XUART(s) Disables a specified TX Enable -N, --canon=PORT(s) Enables a CAN port -f, --canoff=PORT(s) Disables a CAN port -h, --help This help -j, --bbclkon Enables a 12.5MHz clock on DIO 3 -H, --bbclkoff Disables the 12.5MHz clock -E, --bbclk2on Enables a 25MHz clock on DIO 34 -I, --bbclk2off Disables the 25MHz clock -r, --touchon Turns the touchscreen controller on -T, --touchoff Turns the touchscreen controller off -B, --baseboard Display baseboard ID -a, --adc Display MCP3428 ADC readings in millivolts -P, --ethvlan Configures a network switch to split each port individually in a vlan -y, --ethswitch Configures a network switch to switch all of the outside ports to one interface -e, --ethwlan Configures the first network port (A) to its own VLAN, and all other ports to a shared switch -C, --ethinfo Retrieves info on the onboard switch
| Offset | Bits | Usage |
|---|---|---|
| 0x00 | 15:0 | Returns board model, eg 0x4710 = TS-4710 |
| 0x02 | 15 | Reset switch enable (Use DIO 9 input) |
| 14 | Enable touchscreen (override DIO 30-35) | |
| 13 | Enable UART4 TXEN (override DIO 14) | |
| 12 | Enable UART0 TXEN (override DIO 12) | |
| 11 | Enable 12.5MHz base board clock (override DIO 3) | |
| 10 | Enable SPI (override DIO 17-20) | |
| 9 | Enable 2nd CAN (override DIO 10,11) | |
| 8 | Enable CAN (override DIO 15,16) | |
| 7:6 | Scratch Register | |
| 5 | Mode2 | |
| 4 | Mode1 | |
| 3:0 | FPGA revision | |
| 0x04 | 15:0 | Muxbus configuration register |
| 0x06 | 15:0 | Watchdog feed register |
| 0x08 | 15:0 | Free running 1MHz counter LSB |
| 0x0a | 15:0 | Free running 1MHz counter MSB |
| 0x0c | 15:0 | Hardware RNG LSB |
| 0x0e | 15:0 | Hardware RNG MSB |
| 0x10 | 15 | Baseboard 25MHz Clock (override DIO 34) |
| 14:0 | DIO 14:0 output data | |
| 0x12 | 15:14 | Reserved |
| 13 | Enable alternate touch controller pins | |
| 12 | Red LED (1 = on) | |
| 11 | Green LED (1 = on) | |
| 10:6 | DIO 26:22 output data | |
| 5:0 | DIO 20:15 output data | |
| 0x14 | 15:0 | DIO 42:27 output data |
| 0x16 | 15 | Enable UART2 TXEN (override DIO 10) |
| 14 | Enable UART1 TXEN (override DIO 8) | |
| 13 | Enable UART5 TXEN (override DIO 7) | |
| 12 | Enable UART3 TXEN (override DIO 13) | |
| 11:0 | DIO 59:48 output data | |
| 0x18 | 15 | Reserved |
| 14:0 | DIO 14:0 data direction | |
| 0x1a | 15:11 | Reserved |
| 10:6 | DIO 26:22 data direction | |
| 5:0 | DIO 20:15 data direction | |
| 0x1c | 15:0 | DIO 42:27 data direction |
| 0x1e | 15:12 | Reserved |
| 11:0 | DIO 59:48 data direction | |
| 0x20 | 15 | Reserved |
| 14:0 | DIO 14:0 input data | |
| 0x22 | 15:11 | Reserved |
| 10:6 | DIO 26:22 input data | |
| 5:0 | DIO 20:15 input data | |
| 0x24 | 15:0 | DIO 42:27 input data |
| 0x26 | 15:12 | Reserved |
| 11:0 | DIO 59:48 input data | |
| 0x28 | 15:4 | Reserved |
| 3:0 | FPGA TAG memory access [1] | |
| 0x2a | 15:0 | Custom load ID register [2] |
| 0x2c | 15:6 | Reserved |
| 5 | Offboard IRQ 7 | |
| 4 | Offboard IRQ 6 | |
| 3 | Offboard IRQ 5 | |
| 2 | CAN2 IRQ | |
| 1 | CAN IRQ | |
| 0 | XUART IRQ | |
| 0x2e | 15:6 | Reserved |
| 5 | Offboard IRQ 7 mask (1 disabled, 0 on) [3] | |
| 4 | Offboard IRQ 6 mask (1 disabled, 0 on) [3] | |
| 3 | Offboard IRQ 5 mask (1 disabled, 0 on)[3] | |
| 2 | CAN2 IRQ mask (1 disabled, 0 on)[3] | |
| 1 | CAN IRQ mask (1 disabled, 0 on)[3] | |
| 0 | XUART IRQ mask (1 disabled, 0 on)[3] | |
| 0x34 | 0 | Enable 14.3MHz baseboard clock on DIO 3 |
| 1 | USB 5V disable [4] | |
| 2 | LCD 3.3V disable [5] |
- ↑ TAG memory stores persistent data on the FPGA such a the MAC address, CPU settings, and the born on date. Software using this data should instead use tshwctl rather than accessing this register manually.
- ↑ Reads back 0 on default load. Used to identify customized bitstreams
- ↑ 3.0 3.1 3.2 3.3 3.4 3.5 The IRQ masks are handled automatically by the kernel after an IRQ is requested. Under most circumstances these registers should not be manipulated.
- ↑ This toggles a DIO on CN1_04 and requires offboard circuitry on the baseboard to toggle USB power.
- ↑ This toggles a DIO on CN1_48 and requires offboard circuitry on the baseboard to toggle LCD power.