75XX SPIFlash

The SPI flash is also implemented in userspace with NBD, however it is not mounted by default. Even when you are booted to SPI, it does not need to access it directly since the bootrom will load it into memory before the Linux kernel is even executing. If you want to mount any part of it see the spiflashctl page for usage.

This core is for high speed SPI with auto-CS#. Starts at offset 0x40 on the TS-7500. LUN#0 goes to onboard SPI NOR flash chip (TS-7500 only) and LUN#1 goes to offboard SPI (TS-752 or TS-9448 flash chip).

SPI interface register map:

Address Range	Access	Description	Notes
0x40	Read/Write	LUN register	Bits Access Notes 15 Read Only SPI MISO state 14 Read/Write SPI CLK state 13-10 Read/Write speed (0- highest, 1- 1/2 speed, 2- 1/4, 3- 1/6, etc..) 9-8 Read/Write LUN (0-3 representing the 4 CS# signals) 7-0 N/A Reserved
0x42	Read Only	Previous SPI read data from last write
0x44	N/A	Reserved
0x46	N/A	Reserved
0x48	Read/Write	SPI read/write with CS# to stay asserted
0x4a	Read Only	SPI pipelined read with CS# to stay asserted
0x4c	Read/Write	SPI read/write with CS# to deassert post-op
0x4e	N/A	Reserved

The SPI clk state register should be set when CS# is deasserted. Value 0 makes SPI rising edge (CPOL=0), 1 is falling edge (CPOL=1). This only applies to speed >= 1. For speed == 0, SPI clock polarity/skew must be set from the PLL phase adjust registers in the syscon block.

For the TS-75xx/TS-4500 where the base clock is 75Mhz, speed settings break down as follows:

 0 - 75Mhz (/1)
 1 - 37.5Mhz (/2)
 2 - 18.75Mhz (/4)
 3 - 12.5Mhz (/6)
 4 - 9.375Mhz (/8)
 5 - 7.5Mhz (/10)
 6 - 6.25Mhz (/12)
 7 - 5.36Mhz (/14)
 8 - 4.68Mhz (/16)
 9 - 4.17Mhz (/18)
 ...
 15 - 2.5Mhz (/30)

Bits 10-15 were not present on TS-75XX FPGA prior to rev 4. On those TS-75XX's, SPI speed was hardcoded to 75Mhz and 75Mhz only.

The pipelined read register is for read bursts and will automatically start a subsequent SPI read upon completion of the requested SPI read. Reading from this register infers that another read will shortly follow and allows this SPI controller "a head start" on the next read for optimum read performance. This register should be accessed as long as there will be at least one more SPI read with CS# asserted to take place. This register is an appropriate target address for SBUS burst reads.