TS-4100 FPGA DIO Table: Difference between revisions

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(Updated layout with chip and pin numbering for GPIO)
 
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The FPGA IO in Linux are GPIO 160-287.  The crossbar mode indicates what this pin will output from the FPGA's perspective.  For example, by default SPARE_4 outputs the value it samples from the WIFI_IRQ pin.  WIFI_IRQ however is a GPIO so the FPGA can sample the input value.


{| class="wikitable sortable"
{| class="wikitable sortable"
|-
|-
! Schematic Name
! Chip
! GPIO Number
! Pin
! Default Crossbar Mode
! Signal Name
! Location
! Location<ref>GPIO pins are formatted in "<chip>_<pin>" notation.</ref>
! Default Crossbar Input
|-
|-
| SPARE_1
| 5
| 161
| 1
| GPIO (0)
| [[#FPGA_Register|SPARE_1]]
| CPU GPIO (18) UART1_CTS_B
| [[#CPU_GPIO_Table|CPU GPIO 0_18]]
| [[#Crossbar|GPIO]]
|-
|-
| SPARE_2
| 5
| 162
| 2
| GPIO (0)
| [[#FPGA_Register|SPARE_2]]
| CPU GPIO (19) UART1_RTS_B
| [[#CPU_GPIO_Table|CPU GPIO 0_19]]
| [[#Crossbar|GPIO]]
|-
|-
| SPARE_3
| 5
| 163
| 3
| GPIO (0)
| [[#FPGA_Register|SPARE_3]]
| CPU GPIO (112) NAND_DQS
| [[#CPU_GPIO_Table|CPU GPIO 3_16]]
| [[#Crossbar|GPIO]]
|-
|-
| SPARE_4
| 5
| 164
| 4
| WIFI_IRQ (15)
| [[#FPGA_Register|SPARE_4]]
| CPU GPIO  
| [[#CPU_GPIO_Table|CPU GPIO 4_8]]
| [[#Crossbar|WIFI_IRQ]]
|-
|-
| UART3_TXD
| 5
| 165
| 5
| GPIO (0)
| [[#FPGA_Register|UART2_TXD]]
| CPU ttymxc2 TX UART3_TX_DATA
| [[#UARTs|CPU UART2_TXD]]
| [[#Crossbar|GPIO]]
|-
|-
| UART3_RTS
| 5
| 166
| 6
| GPIO (0)
| [[#FPGA_Registers|UART2_CTS#]]
| CPU ttymxc2 RTS UART3_RTS_B
| [[#UARTs|CPU UART2_CTS#]]
| [[#Crossbar|GPIO]]
|-
|-
| UART4_TXD
| 5
| 167
| 7
| GPIO (0)
| [[#FPGA_Regsiters|UART3_TXD]]
| CPU ttymxc3 TX UART4_TX_DATA
| [[#UARTs|CPU UART3_TXD]]
| [[#Crossbar|GPIO]]
|-
|-
| UART7_TXD
| 5
| 168
| 8
| GPIO (0)
| [[#FPGA_Registers|UART6_TXD]]
| CPU ttymxc6 TX LCD_DATA16
| [[#UARTs|CPU UART6_TXD]]
| [[#Crossbar|GPIO]]
|-
|-
| UART3_RXD
| 5
| 169
| 9
| WIFI_RXD (13)
| [[#FPGA_Registers|UART2_RXD]]
| CPU ttymxc2 RX UART3_RX_DATA
| [[#UARTs|CPU UART2_RXD]]
| [[#Crossbar|WIFI_RXD]]
|-
|-
| UART3_CTS
| 5
| 170
| 10
| GPIO (0)
| [[#FPGA_Registers|UART2_RTS#]]
| CPU ttymxc2 CTS UART3_CTS_B
| [[#UARTs|CPU UART2_RTS#]]
| [[#Crossbar|GPIO]]
|-
|-
| UART4_RXD
| 5
| 171
| 11
| UART_A_RXD (29)
| [[#FPGA_Registers|UART3_RXD]]
| CPU ttymxc3 RX UART4_RXD
| [[#UARTs|CPU UART3_RXD]]
| [[#Crossbar|UARTA_RXD]]
|-
|-
| UART7_RXD
| 5
| 172
| 12
| UART_B_RXD (30)
| [[#FPGA_Registers|UART6_RXD]]
| CPU ttymxc6 RX LCD_DATA17
| [[#UARTs|CPU UART6_RXD]]
| [[#Crossbar|UARTB_RXD]]
|-
|-
| WIFI_RXD
| 5
| 173
| 13
| GPIO (0)
| [[#FPGA_Registers|WIFI_RXD]]
| Onboard WIFI RXD
| [[#Bluetooth|Wi-Fi/BT Module TXD]]
| [[#Crossbar|GPIO]]
|-
|-
| WIFI_RTS
| 5
| 174
| 14
| GPIO (0)
| [[#FPGA_Registers|WIFI_RTS#]]
| Onboard WIFI RTS
| [[#Bluetooth|Wi-Fi/BT Module RTS#]]
| [[#Crossbar|GPIO]]
|-
|-
| WIFI_IRQ
| 5
| 175
| 15
| GPIO (0)
| [[#FPGA_Registers|WIFI_IRQ#]]
| Onboard WIFI IRQ
| [[#Wi-Fi|Wi-Fi/BT Module IRQ]]
| [[#Crossbar|GPIO]]
|-
|-
| WIFI_TXD
| 5
| 176
| 16
| UART3_TXD (16)
| [[#FPGA_Registers|WIFI_TXD]]
| Onboard WIFI TXD
| [[#Bluetooth|Wi-Fi/BT Module RXD]]
| [[#Crossbar|UART2_TXD]]
|-
|-
| WIFI_CTS
| 5
| 177
| 17
| UART3_RTS (6)
| [[#FPGA_Registers|WIFI_CTS#]]
| Onboard WIFI CTS
| [[#Bluetooth|Wi-Fi/BT Module CTS#]]
| [[#UARTs|UART2_CTS#]]
|-
|-
| ZPU_BREAK
| 5
| 178
| 18
| GPIO (0)
| [[#FPGA_Registers|ZPU_BREAK]]
| Register
| [[#ZPU|ZPU Output]]
| [[#Crossbar|GPIO]]
|-
|-
| ZPU_RESET
| 5
| 179
| 19
| GPIO (0)
| [[#FPGA_Registers|ZPU_RESET]]
| Register
| [[#ZPU|ZPU Input]]
| [[#Crossbar|GPIO]]
|-
|-
| EN_WIFI_PWR
| 5
| 180
| 20
| GPIO (0)
| [[#FPGA_Registers|EN_WIFI_PWR]]
| Onboard WIFI CHIP_EN
| [[#Wi-Fi|Wi-Fi/BT Module CHIP_EN]]
| [[#Crossbar|GPIO]]
|-
|-
| WIFI_RESET
| 5
| 181
| 21
| GPIO (0)
| [[#FPGA_Registers|WIFI_RESET#]]
| Onboard WIFI RESET
| [[#Wi-Fi|Wi-Fi/BT Module WIFI_RESET#]]
| [[#Crossbar|GPIO]]
|-
|-
| EN_USB_HOST_5V
| 5
| 182
| 22
| GPIO (0)
| [[#FPGA_Registers|EN_USB_HOST_5V]]
| CN1_004
| [[#TS-SOCKET|CN1_004]]
| [[#Crossbar|GPIO]]
|-
|-
| EN_LCD_3V3
| 5
| 183
| 23
| GPIO (0)
| [[#FPGA_Registers|EN_LCD_3V3]]
| CN1_048
| [[#TS-SOCKET|CN1_048]]
| [[#Crossbar|GPIO]]
|-
|-
| EN_SD_POWER_PAD
| 5
| 184
| 24
| GPIO (0)
| [[#FPGA_Registers|ETH_PHY_RESET#]]
| Onboard Regulator
| [[#Ethernet|Ethernet PHY]]
| [[#Crossbar|GPIO]]
|-
|-
| OFF_BD_RESET
| 5
| 185
| 25
| GPIO (0)
| [[#FPGA_Registers|OFF_BD_RESET#]]
| CN1_009
| [[#TS-SOCKET|CN1_009]]
| [[#Crossbar|GPIO]]
|-
|-
| GREEN_LED
| 5
| 187
| 27
| GPIO (0)
| [[#FPGA_Registers|GREEN_LED#]]
| CN2_008
| [[#TS-SOCKET|CN2_008]]
| [[#Crossbar|GPIO]]
|-
|-
| RED_LED
| 5
| 188
| 28
| GPIO (0)
| [[#FPGA_Registers|RED_LED#]]
| CN2_006
| [[#TS-SOCKET|CN2_006]]
| [[#Crossbar|GPIO]]
|-
|-
| UART_A_RXD
| 5
| 189
| 29
| GPIO (0)
| [[#FPGA_Registers|UARTA_RXD]]
| CN2_078
| [[#TS-SOCKET|CN2_078]]
| [[#Crossbar|GPIO]]
|-
|-
| UART_B_RXD
| 5
| 190
| 30
| GPIO (0)
| [[#FPGA_Registers|UARTB_RXD]]
| CN2_088
| [[#TS-SOCKET|CN2_088]]
| [[#Crossbar|GPIO]]
|-
|-
| UART_C_RXD
| 5
| 191
| 31
| GPIO (0)
| [[#FPGA_Registers|UARTC_RXD]]
| CN2_096
| [[#TS-SOCKET|CN2_096]]
| [[#Crossbar|GPIO]]
|-
|-
| UART_D_RXD
| 5
| 192
| 32
| GPIO (0)
| [[#FPGA_Registers|UARTD_RXD]]
| CN2_100
| [[#TS-SOCKET|CN2_100]]
| [[#Crossbar|GPIO]]
|-
|-
| UART_A_TXD_PAD
| 5
| 193
| 33
| UART4_TXD (7)
| [[#FPGA_Registers|UARTA_TXD]]
| CN2_082
| [[#TS-SOCKET|CN2_082]]
| [[#Crossbar|UART3_TXD]]
|-
|-
| UART_B_TXD_PAD
| 5
| 194
| 34
| UART7_TXD (8)
| [[#FPGA_Registers|UARTB_TXD]]
| CN2_086
| [[#TS-SOCKET|CN2_086]]
| [[#Crossbar|UART6_TXD]]
|-
|-
| UART_C_TXD_PAD
| 5
| 195
| 35
| GPIO (0)
| [[#FPGA_Registers|UARTC_TXD]]
| CN2_094
| [[#TS-SOCKET|CN2_094]]
| [[#Crossbar|GPIO]]
|-
|-
| UART_D_TXD_PAD
| 5
| 196
| 36
| GPIO (0)
| [[#FPGA_Registers|UARTD_TXD]]
| CN2_098
| [[#TS-SOCKET|CN2_098]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_00
| 5
| 197
| 37
| GPIO (0)
| [[#FPGA_Registers|DIO_00]]
| CN1_093
| [[#TS-SOCKET|CN1_093]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_01
| 5
| 198
| 38
| GPIO (0)
| [[#FPGA_Registers|DIO_01]]
| CN1_091
| [[#TS-SOCKET|CN1_091]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_02
| 5
| 199
| 39
| GPIO (0)
| [[#FPGA_Registers|DIO_02]]
| CN1_089
| [[#TS-SOCKET|CN1_089]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_03
| 5
| 200
| 40
| GPIO (0)
| [[#FPGA_Registers|DIO_03]]
| CN1_087
| [[#TS-SOCKET|CN1_087]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_04
| 5
| 201
| 41
| GPIO (0)
| [[#FPGA_Registers|DIO_04]]
| CN1_085
| [[#TS-SOCKET|CN1_085]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_05
| 5
| 202
| 42
| GPIO (0)
| [[#FPGA_Registers|DIO_05]]
| CN1_083
| [[#TS-SOCKET|CN1_083]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_06
| 5
| 203
| 43
| GPIO (0)
| [[#FPGA_Registers|DIO_06]]
| CN1_081
| [[#TS-SOCKET|CN1_081]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_07
| 5
| 204
| 44
| GPIO (0)
| [[#FPGA_Registers|DIO_07]]
| CN1_079
| [[#TS-SOCKET|CN1_079]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_08
| 5
| 205
| 45
| GPIO (0)
| [[#FPGA_Registers|DIO_08]]
| CN1_077
| [[#TS-SOCKET|CN1_077]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_09
| 5
| 206
| 46
| GPIO (0)
| [[#FPGA_Registers|DIO_09]]
| CN1_073
| [[#TS-SOCKET|CN1_073]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_12
| 5
| 209
| 49
| GPIO (0)
| [[#FPGA_Registers|DIO_12]]
| CN1_067
| [[#TS-SOCKET|CN1_067]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_13
| 5
| 210
| 50
| GPIO (0)
| [[#FPGA_Registers|DIO_13]]
| CN1_065
| [[#TS-SOCKET|CN1_065]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_14
| 5
| 211
| 51
| GPIO (0)
| [[#FPGA_Registers|DIO_14]]
| CN1_063
| [[#TS-SOCKET|CN1_063]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_15
| 5
| 212
| 52
| GPIO (0)
| [[#FPGA_Registers|DIO_15]]
| CN1_061
| [[#TS-SOCKET|CN1_061]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_16
| 5
| 213
| 53
| GPIO (0)
| [[#FPGA_Registers|DIO_16]]
| CN1_059
| [[#TS-SOCKET|CN1_059]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_17
| 5
| 214
| 54
| GPIO (0)
| [[#FPGA_Registers|DIO_17]]
| CN1_097
| [[#TS-SOCKET|CN1_097]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_18
| 5
| 215
| 55
| GPIO (0)
| [[#FPGA_Registers|DIO_18]]
| CN1_099
| [[#TS-SOCKET|CN1_099]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_19
| 5
| 216
| 56
| GPIO (0)
| [[#FPGA_Registers|DIO_19]]
| CN1_100
| [[#TS-SOCKET|CN1_100]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_20
| 5
| 217
| 57
| GPIO (0)
| [[#FPGA_Registers|DIO_20]]
| CN1_098
| [[#TS-SOCKET|CN1_098]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_21
| 5
| 218
| 58
| GPIO (0)
| [[#FPGA_Registers|DIO_21]]
| CN1_096
| [[#TS-SOCKET|CN1_096]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_22
| 5
| 219
| 59
| GPIO (0)
| [[#FPGA_Registers|DIO_22]]
| CN1_094
| [[#TS-SOCKET|CN1_094]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_23
| 5
| 220
| 60
| GPIO (0)
| [[#FPGA_Registers|DIO_23]]
| CN1_092
| [[#TS-SOCKET|CN1_092]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_24
| 5
| 221
| 61
| GPIO (0)
| [[#FPGA_Registers|DIO_24]]
| CN1_090
| [[#TS-SOCKET|CN1_090]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_25
| 5
| 222
| 62
| GPIO (0)
| [[#FPGA_Registers|DIO_25]]
| CN1_088
| [[#TS-SOCKET|CN1_088]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_26
| 5
| 223
| 63
| GPIO (0)
| [[#FPGA_Registers|DIO_26]]
| CN1_086
| [[#TS-SOCKET|CN1_086]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_27
| 5
| 224
| 64
| GPIO (0)
| [[#FPGA_Registers|DIO_27]]
| CN1_084
| [[#TS-SOCKET|CN1_084]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_28
| 5
| 225
| 65
| GPIO (0)
| [[#FPGA_Registers|DIO_28]]
| CN1_082
| [[#TS-SOCKET|CN1_082]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_29
| 5
| 226
| 66
| GPIO (0)
| [[#FPGA_Registers|DIO_29]]
| CN1_080
| [[#TS-SOCKET|CN1_080]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_30
| 5
| 227
| 67
| GPIO (0)
| [[#FPGA_Registers|DIO_30]]
| CN1_078
| [[#TS-SOCKET|CN1_078]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_31
| 5
| 228
| 68
| GPIO (0)
| [[#FPGA_Registers|DIO_31]]
| CN1_076
| [[#TS-SOCKET|CN1_076]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_32
| 5
| 229
| 69
| GPIO (0)
| [[#FPGA_Registers|DIO_32]]
| CN1_074
| [[#TS-SOCKET|CN1_074]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_33
| 5
| 230
| 70
| GPIO (0)
| [[#FPGA_Registers|DIO_33]]
| CN1_072
| [[#TS-SOCKET|CN1_072]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_34
| 5
| 231
| 71
| GPIO (0)
| [[#FPGA_Registers|DIO_34]]
| CN1_070
| [[#TS-SOCKET|CN1_070]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_35
| 5
| 232
| 72
| GPIO (0)
| [[#FPGA_Registers|DIO_35]]
| CN1_068
| [[#TS-SOCKET|CN1_068]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_36
| 5
| 233
| 73
| GPIO (0)
| [[#FPGA_Registers|DIO_36]]
| CN1_066
| [[#TS-SOCKET|CN1_066]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_37
| 5
| 234
| 74
| GPIO (0)
| [[#FPGA_Registers|DIO_37]]
| CN1_064
| [[#TS-SOCKET|CN1_064]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_38
| 5
| 235
| 75
| GPIO (0)
| [[#FPGA_Registers|DIO_38]]
| CN1_060
| [[#TS-SOCKET|CN1_060]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_39
| 5
| 236
| 76
| GPIO (0)
| [[#FPGA_Registers|DIO_39]]
| CN1_058
| [[#TS-SOCKET|CN1_058]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_41
| 5
| 238
| 78
| GPIO (0)
| [[#FPGA_Registers|DIO_41]]
| CN1_024
| [[#TS-SOCKET|CN1_024]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_42
| 5
| 239
| 79
| GPIO (0)
| [[#FPGA_Registers|DIO_42]]
| CN1_026
| [[#TS-SOCKET|CN1_026]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_43
| 5
| 240
| 80
| GPIO (0)
| [[#FPGA_Registers|DIO_43]]
| CN1_019
| [[#TS-SOCKET|CN1_019]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_44
| 5
| 241
| 81
| GPIO (0)
| [[#FPGA_Registers|DIO_44]]
| CN1_021
| [[#TS-SOCKET|CN1_021]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_45
| 5
| 242
| 82
| GPIO (0)
| [[#FPGA_Registers|DIO_45]]
| CN1_037
| [[#TS-SOCKET|CN1_037]]
| [[#Crossbar|GPIO]]
|-
|-
| DIO_46
| 5
| 243
| 83
| GPIO (0)
| [[#FPGA_Registers|DIO_46]]
| CN1_039
| [[#TS-SOCKET|CN1_039]]
| [[#Crossbar|GPIO]]
|}
|}
<references/>

Latest revision as of 15:07, 25 June 2019

Chip Pin Signal Name Location[1] Default Crossbar Input
5 1 SPARE_1 CPU GPIO 0_18 GPIO
5 2 SPARE_2 CPU GPIO 0_19 GPIO
5 3 SPARE_3 CPU GPIO 3_16 GPIO
5 4 SPARE_4 CPU GPIO 4_8 WIFI_IRQ
5 5 UART2_TXD CPU UART2_TXD GPIO
5 6 UART2_CTS# CPU UART2_CTS# GPIO
5 7 UART3_TXD CPU UART3_TXD GPIO
5 8 UART6_TXD CPU UART6_TXD GPIO
5 9 UART2_RXD CPU UART2_RXD WIFI_RXD
5 10 UART2_RTS# CPU UART2_RTS# GPIO
5 11 UART3_RXD CPU UART3_RXD UARTA_RXD
5 12 UART6_RXD CPU UART6_RXD UARTB_RXD
5 13 WIFI_RXD Wi-Fi/BT Module TXD GPIO
5 14 WIFI_RTS# Wi-Fi/BT Module RTS# GPIO
5 15 WIFI_IRQ# Wi-Fi/BT Module IRQ GPIO
5 16 WIFI_TXD Wi-Fi/BT Module RXD UART2_TXD
5 17 WIFI_CTS# Wi-Fi/BT Module CTS# UART2_CTS#
5 18 ZPU_BREAK ZPU Output GPIO
5 19 ZPU_RESET ZPU Input GPIO
5 20 EN_WIFI_PWR Wi-Fi/BT Module CHIP_EN GPIO
5 21 WIFI_RESET# Wi-Fi/BT Module WIFI_RESET# GPIO
5 22 EN_USB_HOST_5V CN1_004 GPIO
5 23 EN_LCD_3V3 CN1_048 GPIO
5 24 ETH_PHY_RESET# Ethernet PHY GPIO
5 25 OFF_BD_RESET# CN1_009 GPIO
5 27 GREEN_LED# CN2_008 GPIO
5 28 RED_LED# CN2_006 GPIO
5 29 UARTA_RXD CN2_078 GPIO
5 30 UARTB_RXD CN2_088 GPIO
5 31 UARTC_RXD CN2_096 GPIO
5 32 UARTD_RXD CN2_100 GPIO
5 33 UARTA_TXD CN2_082 UART3_TXD
5 34 UARTB_TXD CN2_086 UART6_TXD
5 35 UARTC_TXD CN2_094 GPIO
5 36 UARTD_TXD CN2_098 GPIO
5 37 DIO_00 CN1_093 GPIO
5 38 DIO_01 CN1_091 GPIO
5 39 DIO_02 CN1_089 GPIO
5 40 DIO_03 CN1_087 GPIO
5 41 DIO_04 CN1_085 GPIO
5 42 DIO_05 CN1_083 GPIO
5 43 DIO_06 CN1_081 GPIO
5 44 DIO_07 CN1_079 GPIO
5 45 DIO_08 CN1_077 GPIO
5 46 DIO_09 CN1_073 GPIO
5 49 DIO_12 CN1_067 GPIO
5 50 DIO_13 CN1_065 GPIO
5 51 DIO_14 CN1_063 GPIO
5 52 DIO_15 CN1_061 GPIO
5 53 DIO_16 CN1_059 GPIO
5 54 DIO_17 CN1_097 GPIO
5 55 DIO_18 CN1_099 GPIO
5 56 DIO_19 CN1_100 GPIO
5 57 DIO_20 CN1_098 GPIO
5 58 DIO_21 CN1_096 GPIO
5 59 DIO_22 CN1_094 GPIO
5 60 DIO_23 CN1_092 GPIO
5 61 DIO_24 CN1_090 GPIO
5 62 DIO_25 CN1_088 GPIO
5 63 DIO_26 CN1_086 GPIO
5 64 DIO_27 CN1_084 GPIO
5 65 DIO_28 CN1_082 GPIO
5 66 DIO_29 CN1_080 GPIO
5 67 DIO_30 CN1_078 GPIO
5 68 DIO_31 CN1_076 GPIO
5 69 DIO_32 CN1_074 GPIO
5 70 DIO_33 CN1_072 GPIO
5 71 DIO_34 CN1_070 GPIO
5 72 DIO_35 CN1_068 GPIO
5 73 DIO_36 CN1_066 GPIO
5 74 DIO_37 CN1_064 GPIO
5 75 DIO_38 CN1_060 GPIO
5 76 DIO_39 CN1_058 GPIO
5 78 DIO_41 CN1_024 GPIO
5 79 DIO_42 CN1_026 GPIO
5 80 DIO_43 CN1_019 GPIO
5 81 DIO_44 CN1_021 GPIO
5 82 DIO_45 CN1_037 GPIO
5 83 DIO_46 CN1_039 GPIO
  1. ↑ GPIO pins are formatted in "<chip>_<pin>" notation.
Retrieved from "http://docs.embeddedTS.com/index.php?title=TS-4100_FPGA_DIO_Table&oldid=10589"