TS-7180 CPU SPI Controller: Difference between revisions
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The i.MX6UL CPU has a native SPI peripheral that is used in a number of places on the TS-7180. Additionally, kernel spidev support is added to allow SPI access from userspace. User SPI can be used fora generic SPI connection on [[# | The i.MX6UL CPU has a native SPI peripheral that is used in a number of places on the TS-7180. Additionally, kernel spidev support is added to allow SPI access from userspace. User SPI can be used fora generic SPI connection on [[#HD12_Header|HD12]], as well as [[#FRAM|user accessible FRAM]]. | ||
The ECSPI peripheral in the i.MX6UL CPU is highly flexible and can even support SPI slave mode. For more information on the peripheral itself, please see the [http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf CPU reference manual]. | The ECSPI peripheral in the i.MX6UL CPU is highly flexible and can even support SPI slave mode. For more information on the peripheral itself, please see the [http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf CPU reference manual]. | ||
The SPI peripheral is accessible as /dev/spidev2.x, where x is one of the three chip select lines. Additional chip select lines can be implemented if needed by adding them to the kernel device-tree by using GPIO. | The SPI peripheral is accessible as <code>/dev/spidev2.x</code>, where "x" is one of the three chip select lines. Additional chip select lines can be implemented if needed by adding them to the kernel device-tree by using GPIO. | ||
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Latest revision as of 11:17, 11 May 2023
The i.MX6UL CPU has a native SPI peripheral that is used in a number of places on the TS-7180. Additionally, kernel spidev support is added to allow SPI access from userspace. User SPI can be used fora generic SPI connection on HD12, as well as user accessible FRAM.
The ECSPI peripheral in the i.MX6UL CPU is highly flexible and can even support SPI slave mode. For more information on the peripheral itself, please see the CPU reference manual.
The SPI peripheral is accessible as /dev/spidev2.x, where "x" is one of the three chip select lines. Additional chip select lines can be implemented if needed by adding them to the kernel device-tree by using GPIO.
| CS | Device |
|---|---|
| 0 | Reserved for FPGA |
| 1 | HD12 |
| 2 | FRAM |
See the kernel spidev documentation for more information on interfacing with the SPI peripherals.