TS-7250-V3 DIO Header: Difference between revisions
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The DIO header is a 0.1" pitch 2x8 header including SPI and GPIO. | The DIO header is a 0.1" pitch 2x8 header including SPI and GPIO. All pins on this header are 5V tolerant except SPI output pins. The SPI input pins are 5V tolerant and can be connected to a 5V SPI device. All of these DIO include pullups. | ||
{| | {| | ||
Line 9: | Line 9: | ||
|- | |- | ||
! Pin | ! Pin | ||
! IO Type | |||
! Signal | ! Signal | ||
|- | |- | ||
| 1 | | 1 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 1]] | |||
|- | |- | ||
| 2 | | 2 | ||
| | |||
| GND | | GND | ||
|- | |- | ||
| 3 | | 3 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 2]] | |||
|- | |- | ||
| 4 | | 4 | ||
| [[#GPIO|Current Sink Output | | Open drain<ref>High drives ground, low is tristate. </ref> | ||
| [[#GPIO|Current Sink Output Chip 209c000.gpio IO 30]] | |||
|- | |- | ||
| 5 | | 5 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 3]] / [[#UARTs|ttyS14 TX]] | |||
|- | |- | ||
| 6 | | 6 | ||
| [[#SPI|spidev 0 | | [[#IO specifications|FPGA 3.3-V LVTTL]] | ||
| [[#SPI|spidev 4.0 Chip Select]] / [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 11]] | |||
|- | |- | ||
| 7 | | 7 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 4]] / [[#UARTs|ttyS14 RX]] | |||
|- | |- | ||
| 8 | | 8 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 5]] | |||
|- | |- | ||
| 9 | | 9 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 6]] / [[#UARTs|ttyS15 TX]] | |||
|- | |- | ||
| 10 | | 10 | ||
| [[#SPI|spidev 0. | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#SPI|spidev 4.0 MISO]] / [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 10]] <ref>This pin is input only even when in the GPIO mode</ref> | |||
|- | |- | ||
| 11 | | 11 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 7]] / [[#UARTs|ttyS15 RX]] | |||
|- | |- | ||
| 12 | | 12 | ||
| [[#SPI|spidev 0. | | [[#IO specifications|FPGA 3.3-V LVTTL]] | ||
| [[#SPI|spidev 4.0 MOSI]] / [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 15]] | |||
|- | |- | ||
| 13 | | 13 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 8]] / [[#UARTs|ttyS14 TXEN]] | |||
|- | |- | ||
| 14 | | 14 | ||
| [[#SPI|spidev 0. | | [[#IO specifications|FPGA 3.3-V LVTTL]] | ||
| [[#SPI|spidev 4.0 CLK]] / [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 14]] | |||
|- | |- | ||
| 15 | | 15 | ||
| [[#GPIO|GPIO | | [[#IO specifications|FPGA 3.3-V LVTTL+QS3861]] | ||
| [[#GPIO|GPIO Chip 50004010.fpga_gpio IO 9]] / [[#UARTs|ttyS15 TXEN]] | |||
|- | |- | ||
| 16 | | 16 | ||
| | |||
| [[#Board Rails|3.3V]] | | [[#Board Rails|3.3V]] | ||
|} | |} | ||
Line 64: | Line 81: | ||
<References /> | <References /> | ||
[[File:KPAD.jpg|200px|right]] | |||
To use the SPI pins on this header as GPIO instead, disable SPI by changing the [[#FPGA Syscon|FPGA Syscon 0x08 bit 10]]: | |||
<source lang=bash> | |||
tshwctl -a 0x8 --poke32 0x400 | |||
</source> | |||
The DIO header is designed to provide compatibility with the KPAD accessory. This is a 4x4 numerical keypad. This is supported in userspace with the [https://github.com/embeddedTS/ts7100-utils/blob/master/src/keypad.c keypad.c] source code, or the "keypad" utility which is included in the shiping image. | |||
This debounces presses to 50ms, and does not repeat when numbers are held. This will output a string containing the key that is pressed. Eg: | |||
<console> | |||
root@tsimx6:~# keypad | |||
1 | |||
UP | |||
DOWN | |||
2ND | |||
ENTER | |||
</console> |
Latest revision as of 10:54, 9 April 2024
The DIO header is a 0.1" pitch 2x8 header including SPI and GPIO. All pins on this header are 5V tolerant except SPI output pins. The SPI input pins are 5V tolerant and can be connected to a 5V SPI device. All of these DIO include pullups.
To use the SPI pins on this header as GPIO instead, disable SPI by changing the FPGA Syscon 0x08 bit 10:
tshwctl -a 0x8 --poke32 0x400
The DIO header is designed to provide compatibility with the KPAD accessory. This is a 4x4 numerical keypad. This is supported in userspace with the keypad.c source code, or the "keypad" utility which is included in the shiping image.
This debounces presses to 50ms, and does not repeat when numbers are held. This will output a string containing the key that is pressed. Eg:
root@tsimx6:~# keypad 1 UP DOWN 2ND ENTER