TS-7250-V3 DIO Header: Difference between revisions

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| 6
| 6
| [[#SPI|spidev 4.0 Chip Select]]
| [[#SPI|spidev 4.0 Chip Select]] / [[#GPIO|GPIO Bank 5 IO 11]]
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| 7
| 7
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| 10
| 10
| [[#SPI|spidev 4.0 MISO]]
| [[#SPI|spidev 4.0 MISO]] / [[#GPIO|GPIO Bank 5 IO 10]] <ref>This pin is input only even when in the GPIO mode</ref>
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| 11
| 11
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| 12
| 12
| [[#SPI|spidev 4.0 MOSI]]
| [[#SPI|spidev 4.0 MOSI]] / [[#GPIO|GPIO Bank 5 IO 15]]
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| 13
| 13
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| 14
| 14
| [[#SPI|spidev 4.0 CLK]]
| [[#SPI|spidev 4.0 CLK]] / [[#GPIO|GPIO Bank 5 IO 14]]
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| 15
| 15

Revision as of 10:31, 21 July 2022

The DIO header is a 0.1" pitch 2x8 header including SPI and GPIO. All pins on this header are 5V tolerant except SPI output pins. All of these DIO includes pullups.

Signals Pin Layout
Pin Signal
1 GPIO Bank 5 IO 1
2 GND
3 GPIO Bank 5 IO 2
4 Current Sink Output Bank 0 IO 30 [1]
5 GPIO Bank 5 IO 3 / ttyS14 TX
6 spidev 4.0 Chip Select / GPIO Bank 5 IO 11
7 GPIO Bank 5 IO 4 / ttyS14 RX
8 GPIO Bank 5 IO 5
9 GPIO Bank 5 IO 6 / ttyS15 TX
10 spidev 4.0 MISO / GPIO Bank 5 IO 10 [2]
11 GPIO Bank 5 IO 7 / ttyS15 RX
12 spidev 4.0 MOSI / GPIO Bank 5 IO 15
13 GPIO Bank 5 IO 8 / ttyS14 TXEN
14 spidev 4.0 CLK / GPIO Bank 5 IO 14
15 GPIO Bank 5 IO 9 / ttyS15 TXEN
16 3.3V

TS-7250-V3-DIO Header.svg

  1. When this pin is a high output it enables a FET to ground.
  2. This pin is input only even when in the GPIO mode
KPAD.jpg

The DIO header is designed to provide compatibility with the KPAD accessory. This is a 4x4 numerical keypad. This is supported in userspace with the keypad.c source code, or the "keypad" utility which is included in the shiping image.

This debounces presses to 50ms, and does not repeat when numbers are held. This will output a string containing the key that is pressed. Eg:

root@tsimx6:~# keypad
1
UP
DOWN
2ND
ENTER