TS-8100 MUXBUS: Difference between revisions
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The MUXBUS is the bus between the FPGA on the | The MUXBUS is the bus between the FPGA on the SoM to communicate with the off-board CPLD. The CPLD controls PC/104 access as well as some DIO. The MUXBUS config register in the [[#Syscon|Syscon]] allows enabling and configuring the speed for this bus. The MUXBUS timing also influences the communication with PC/104 peripherals. | ||
For more advanced details on the MUXBUS, refer to the implementation details [[Generic_MUXBUS|here]]. | For more advanced details on the MUXBUS, refer to the implementation details [[Generic_MUXBUS|here]]. | ||
Latest revision as of 16:34, 20 February 2023
The MUXBUS is the bus between the FPGA on the SoM to communicate with the off-board CPLD. The CPLD controls PC/104 access as well as some DIO. The MUXBUS config register in the Syscon allows enabling and configuring the speed for this bus. The MUXBUS timing also influences the communication with PC/104 peripherals.
For more advanced details on the MUXBUS, refer to the implementation details here.