TS-4100 TS-Socket
From embeddedTS Manuals
- ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported.
- ↑ EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
- ↑ This is an output which can be manipulated as a GPIO. This pin can optionally be connected to control a FET to a separate 5 V rail for USB to allow software to reset USB devices. Many of our baseboards implement this.
- ↑ OFF_BD_RESET# is an output from the SoM that automatically sends a reset signal when the unit powers up or reboots. It can be connected to any IC on the base board that requires a reset.
- ↑ 5.0 5.1 This interface is for programming the on-board microcontroller, this should be left unconnected on a baseboard.
- ↑ 6.0 6.1 6.2 6.3 The power pins should each be provided with a 5 V source.
- ↑ This is a multi-purpose pin, part of the FPGA Crossbar MUX. The CPU and FPGA pins are connected in parallel.
- ↑ When low, overrides the microcontroller power control and enables 5 V rail on the TS-4100. Leave unconnected for normal use.
- ↑ This is an output that can be manipulated as a GPIO.
- ↑ 10.0 10.1 Allows the supervisory microcontroller to measure USB VBUS for the OTG port.
- ↑ When held high during CPU startup, enables i.MX6UL USB Boot bootloader.
- ↑ 12.0 12.1 12.2 12.3 This pin is part of the FPGA Crossbar MUX. Its default Crossbar assignment is listed first, with the Crossbar name in parenthesis.