TS-7250-V2 FPGA Changelog

FPGA Revision Log

Revision	Changes
13	Connected EN_USB_5V to FPGA logic.
10, 11, 12	Internal unpublished releases.
9	Connect RX line for XUART 4.
8	Fix blockram arbiter for XUARTs.
7	Workaround for TS-ADC16 ISA bus cycles (extra hold time on writes)
6	At TS's special 16-bit ISA pin mapping on the PC104 64 pin connector and make it the default.
5	Fix ISA 8-bit cycles at the 0x81xx_xxxx chip-select
4	Mask 14mhz clk into EVGPIO core Make IO PC104 bus cycles the default, evgpio bit must be used to enable MEMR/W Fix red/green LED reg bit positions to be compatible with 47xx
3	Pullups on LCD/DIO/PC104 pins Console enable on DB9 via JP2 Split IO/MEM PC104 region soft JP #7 now keeps PXA168s at 800Mhz IO bus cycles now drive upper address lines to 0 Inverted isa_16bit_en bit so that the poweron default is enabled
2	EVGPIO IRQ fixup
1	Fixed ISA databus
0	Initial release

You can update to the revision 9 opencore FPGA by booting to Debian and running:

cd /ts/
wget ftp://ftp.embeddedTS.com/ts-arm-sbc/ts-7250-v2-linux/binaries/ts-bitstreams/ts7250v2-rev9-6xuart.vme.bz2
mv /ts/ts7250v2-rev9-6xuart.vme.bz2 /ts/ts7250-fpga.vme.bz2

The FPGA is loaded in to the FPGA SRAM on every load, so this file will need to exist for all future boots.