TS-7600 Syscon: Difference between revisions

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All of the registers below are 16bits wide and must be accessed through the NBUS.  This can either be done directly via tshwctl to read/write the registers, or using some of the options to tshwctl to change them.  Another method is to manipulate the registers via C code using our NBUS API, see the [[#Accessing_Hardware_Registers|Hardware Registers]] section for more information.
{| class=wikitable
{| class=wikitable
! Offset
! Offset
Line 22: Line 24:
|-
|-
| 10
| 10
| Reserved latched mode3 value
| Enable CAN on DIO pins
|-
|-
| 9
| 9
| Reserved latched mode2 value
| Reserved
|-
|-
| 8
| 8
| Reserved latched mode1 value
| Latched mode1 value
|-
|-
| 7:4
| 7:4
Line 58: Line 60:
| 0x8
| 0x8
| 15:0
| 15:0
| DIO 15:0 input data
| [[#DIO|DIO 15:0 input data]]
|-
|-
| 0xa
| 0xa
| 15:0
| 15:0
| DIO 15:0 output data
| [[#DIO|DIO 15:0 output data]]
|-
|-
| 0xc
| 0xc
| 15:0
| 15:0
| DIO 15:0 data direction (1 - output)
| [[#DIO|DIO 15:0 data direction (1 - output)]]
|-
|-
| 0xe
| 0xe
| 15:0
| 15:0
| DIO 31:16 input data
| [[#DIO|DIO 31:16 input data]]
|-
|-
| 0x10
| 0x10
| 15:0
| 15:0
| DIO 31:16 output data
| [[#DIO|DIO 31:16 output data]]
|-
|-
| 0x12
| 0x12
| 15:0
| 15:0
| DIO 31:16 data direction (1 - output)
| [[#DIO|DIO 31:16 data direction (1 - output)]]
|-
|-
| 0x14
| 0x14
| 15:0
| 15:0
| DIO 47:32 input data
| [[#DIO|DIO 47:32 input data]]
|-
|-
| 0x16
| 0x16
| 15:0
| 15:0
| DIO 47:32 output data
| [[#DIO|DIO 47:32 output data]]
|-
|-
| 0x18
| 0x18
| 15:0
| 15:0
| DIO 47:32 data direction (1 - output)
| [[#DIO|DIO 47:32 data direction (1 - output)]]
|-
|-
| 0x1a
| 0x1a
| 15:0
| 15:0
| DIO 63:48 input data
| [[#DIO|DIO 63:48 input data]]
|-
|-
| 0x1c
| 0x1c
| 15:0
| 15:0
| DIO 63:48 output data
| [[#DIO|DIO 63:48 output data]]
|-
|-
| 0x1e
| 0x1e
| 15:0
| 15:0
| DIO 53:48 data direction (1 - output)
| [[#DIO|DIO 63:48 data direction (1 - output)]]
|-
| rowspan=2 | 0x20
| 15:6
| Reserved
|-
| 5:0
| [[#DIO|DIO 69:64 input data]]
|-
| rowspan=2 | 0x22
| 15:6
| Reserved
|-
|-
| rowspan=4 | 0x20
| 5:0
| 15:9
| [[#DIO|DIO 69:64 output data]]
|-
| rowspan=2 | 0x24
| 15:6
| Reserved
| Reserved
|-
|-
| 8:6
| 5:0
| DIO 66:64 input data
| [[#DIO|DIO 69:64 data direction (1 - output)]]
|-
|-
| 5:3
| 0x26
| DIO 66:64 output data
| 16:0
| [[#EVGPIO|EVGPIO Data register]]
|-
|-
| 2:0
| 0x28
| DIO 66:64 data direction (1 - output)
| 16:0
| [[#EVGPIO|EVGPIO Data Direction register]]
|-
|-
| 0x22
| 0x2a
| 15:0
| 15:0
| [[#Watchdog]]
| [[#Watchdog|Watchdog]]
|-
| 0x2c
| 15:0
| Reserved
|-
| rowspan=7 | 0x2e
| 15:14
| Reserved
|-
| 13
| SD#1 LED blink enable
|-
| 12
| SD#1 LED enable
|-
| 11
| SD#0 LED blink enable
|-
| 10
| SD#0 LED enable
|-
| 9:8
| Reserved
|-
|-
| 7:0
| [[#XUARTs|Override DIO and use as TXEN for respective XUART]]
|}
|}


<references />
<references />

Latest revision as of 11:41, 14 March 2022

All of the registers below are 16bits wide and must be accessed through the NBUS. This can either be done directly via tshwctl to read/write the registers, or using some of the options to tshwctl to change them. Another method is to manipulate the registers via C code using our NBUS API, see the Hardware Registers section for more information.

Offset Bits Usage
0x0 15:0 Model ID: Reads 0x7600
0x2 15 Green LED (1 - on)
14 Red LED (1 - on)
13-12 Scratch Reg
11 Reset Switch Enable (1 - reboot when dio9 low)
10 Enable CAN on DIO pins
9 Reserved
8 Latched mode1 value
7:4 Board Submodel (0x0 on production units)
3:0 FPGA revision
0x4 15:0 Random data changed every 1 second
0x6 15:4 Reserved
3 Lattice tagmem clock
2 Lattice tagmem serial in
1 Lattice tagmem CSn
0 Lattice tagmem serial out
0x8 15:0 DIO 15:0 input data
0xa 15:0 DIO 15:0 output data
0xc 15:0 DIO 15:0 data direction (1 - output)
0xe 15:0 DIO 31:16 input data
0x10 15:0 DIO 31:16 output data
0x12 15:0 DIO 31:16 data direction (1 - output)
0x14 15:0 DIO 47:32 input data
0x16 15:0 DIO 47:32 output data
0x18 15:0 DIO 47:32 data direction (1 - output)
0x1a 15:0 DIO 63:48 input data
0x1c 15:0 DIO 63:48 output data
0x1e 15:0 DIO 63:48 data direction (1 - output)
0x20 15:6 Reserved
5:0 DIO 69:64 input data
0x22 15:6 Reserved
5:0 DIO 69:64 output data
0x24 15:6 Reserved
5:0 DIO 69:64 data direction (1 - output)
0x26 16:0 EVGPIO Data register
0x28 16:0 EVGPIO Data Direction register
0x2a 15:0 Watchdog
0x2c 15:0 Reserved
0x2e 15:14 Reserved
13 SD#1 LED blink enable
12 SD#1 LED enable
11 SD#0 LED blink enable
10 SD#0 LED enable
9:8 Reserved
7:0 Override DIO and use as TXEN for respective XUART


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