Imx6ul Ethernet: Difference between revisions
From embeddedTS Manuals
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The NXP iMX6.UL processor implements two 10/100 Ethernet controllers via external Microchip/Micrel KSZ8081 PHYs and dual RJ45 jacks at the edge of the board. Their MAC address addresses will always be sequential and are assigned from a Technologic Systems pool (e8:1a:58 or 00:d0:69). | The NXP iMX6.UL processor implements two 10/100 Ethernet controllers via external Microchip/Micrel KSZ8081 PHYs and dual RJ45 jacks at the edge of the board. Their MAC address addresses will always be sequential and are assigned from a Technologic Systems pool (e8:1a:58 or 00:d0:69). | ||
Support is built into U-Boot as well as the Linux kernel, where standard utilities such as <code>ifconfig/ip</code> can be used to control these interfaces. See the [[# | Support is built into U-Boot as well as the Linux kernel, where standard utilities such as <code>ifconfig/ip</code> can be used to control these interfaces. See the [[#Debian_10_-_Configuring the Network|Configuring the Network]] section for more details. The [[#I.MX6ul_PTP_support|Precision Time Protocol (PTP)]] is also supported. For further specifics of this controller, see the [http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/i.mx6qp/i.mx-6ultralite-processor-low-power-secure-arm-cortex-a7-core:i.MX6UL?fpsp=1&tab=Documentation_Tab# CPU manual]. | ||
Revision as of 12:23, 16 March 2023
The NXP iMX6.UL processor implements two 10/100 Ethernet controllers via external Microchip/Micrel KSZ8081 PHYs and dual RJ45 jacks at the edge of the board. Their MAC address addresses will always be sequential and are assigned from a Technologic Systems pool (e8:1a:58 or 00:d0:69).
Support is built into U-Boot as well as the Linux kernel, where standard utilities such as ifconfig/ip can be used to control these interfaces. See the Configuring the Network section for more details. The Precision Time Protocol (PTP) is also supported. For further specifics of this controller, see the CPU manual.