TS-4900 TS-Socket: Difference between revisions

From embeddedTS Manuals
(Created page with "{| ! CN1 ! CN2 |- | {| class=wikitable ! Name ! Pin ! ! Pin ! Name |- | Reserved | 1 ! | 2 | EXT_RESET# <ref>EXT_RESET# is an input used to reboot the CPU. Do not drive acti...")
 
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! Name
! Name
|-
|-
| Reserved
| NC
| 1
| 1
!
!
Line 17: Line 17:
| EXT_RESET# <ref>EXT_RESET# is an input used to reboot the CPU.  Do not drive active high, use open drain. </ref>
| EXT_RESET# <ref>EXT_RESET# is an input used to reboot the CPU.  Do not drive active high, use open drain. </ref>
|-
|-
| Reserved
| NC
| 3
| 3
! C
! C
Line 23: Line 23:
| EN_USB_5V <ref>This is an output which can be manipulated in the [[#Syscon]].  This pin can optionally be connected to control a FET to a separate 5V rail for USB to allow software to reset USB devices.</ref>
| EN_USB_5V <ref>This is an output which can be manipulated in the [[#Syscon]].  This pin can optionally be connected to control a FET to a separate 5V rail for USB to allow software to reset USB devices.</ref>
|-
|-
| Reserved
| NC
| 5
| 5
! N
! N
Line 29: Line 29:
| [[#SD Card Interface|SD2_D2]] <ref name=sdinterface>This SD interface is the same one used by the MicroSD on the TS-4900.  Only one can be used at a time.  </ref>
| [[#SD Card Interface|SD2_D2]] <ref name=sdinterface>This SD interface is the same one used by the MicroSD on the TS-4900.  Only one can be used at a time.  </ref>
|-
|-
| Reserved
| NC
| 7
| 7
! 1
! 1
Line 41: Line 41:
| [[#SD Card Interface|SD2_CMD]] <ref name=sdinterface />
| [[#SD Card Interface|SD2_CMD]] <ref name=sdinterface />
|-
|-
| Reserved
| NC
| 11
| 11
!
!
Line 47: Line 47:
| 3.3V
| 3.3V
|-
|-
| Reserved
| NC
| 13
| 13
! C
! C
Line 59: Line 59:
| 5V  <ref name=powerpins />
| 5V  <ref name=powerpins />
|-
|-
| Reserved
| NC
| 17
| 17
! 1
! 1
Line 75: Line 75:
!
!
| 22
| 22
| Reserved
| NC
|-
|-
| [[#LCD Interface|LCD_D10]]
| [[#LCD Interface|LCD_D10]]
Line 159: Line 159:
!
!
| 50
| 50
| Reserved
| NC
|-
|-
| [[#LCD Interface|LCD_HSYNC]]
| [[#LCD Interface|LCD_HSYNC]]
Line 320: Line 320:
! Name
! Name
|-
|-
| [[#Ethernet Port|ETH_RX+]]
| [[#Ethernet Port|MDI_0_P]]
| 1
| 1
!
!
| 2
| 2
| [[#Ethernet Port|ETH_LEFT_LED]]
| [[#Ethernet Port|ETH_ACT_LED]]
|-
|-
| [[#Ethernet Port|ETH_RX-]]
| [[#Ethernet Port|MDI_0_M]]
| 3
| 3
! C
! C
| 4
| 4
| [[#Ethernet Port|ETH_RIGHT_LED]]
| [[#Ethernet Port|ETH_LINK_LED]]
|-
|-
| [[#Ethernet Port|ETH_CT]]
| [[#Ethernet Port|ETH_CT]]
Line 338: Line 338:
| [[#LEDs|RED_LED#]]
| [[#LEDs|RED_LED#]]
|-
|-
| [[#Ethernet Port|ETH_TX+]]
| [[#Ethernet Port|MDI_1_P]]
| 7
| 7
! 2
! 2
Line 344: Line 344:
| [[#LEDs|GREEN_LED#]]
| [[#LEDs|GREEN_LED#]]
|-
|-
| [[#Ethernet Port|ETH_TX-]]
| [[#Ethernet Port|MDI_1_M]]
| 9
| 9
!
!
| 10
| 10
| [[#GPIO|MFP_105]]
| [[#LVDS|LVDS_TX3_P]]
|-
|-
| [[#Ethernet Port|ETH_CT]]
| [[#Ethernet Port|ETH_CT]]
Line 354: Line 354:
!
!
| 12
| 12
| [[#GPIO|MFP_106]]
| [[#LVDS|LVDS_TX3_N]]
|-
|-
| 3.3V <ref name=power-threethree>The TS-4710 regulates a 3.3V rail which can source up to 700mA.  Designs should target a 300mA max if they intend to use other macrocontrollers.</ref>
| 3.3V <ref name=power-threethree>The TS-4900 regulates a 3.3V rail which can source up to 700mA.  Designs should target a 300mA max if they intend to use other macrocontrollers.</ref>
| 13
| 13
! C
! C
| 14
| 14
| [[#GPIO|MFP_122]]
| Ground
|-
|-
| Ground
| Ground
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! N
! N
| 16
| 16
| Reserved
| [[#LVDS|LVDS_TX2_P]]
|-
|-
| Reserved
| [[#Ethernet Port|MDI_2_P]]
| 17
| 17
! 2
! 2
| 18
| 18
| Reserved
| [[#LVDS|LVDS_TX2_P]]
|-
|-
| Reserved
| [[#Ethernet Port|MDI_2_N]]
| 19
| 19
!
!
| 20
| 20
| Reserved
| NC
|-
|-
| Ground
| Ground
Line 384: Line 384:
!
!
| 22
| 22
| Reserved
| [[#LVDS|LVDS_TX0_P]]
|-
|-
| Reserved
| [[#Ethernet Port|MDI_3_P]]
| 23
| 23
! C
! C
| 24
| 24
| Reserved
| NC
|-
|-
| Reserved
| [[#Ethernet Port|MDI_3_N]]
| 25
| 25
! N
! N
| 26
| 26
| [[#GPIO|MFP_49]]
| NC
|-
|-
| Reserved
| 1.2V
| 27
| 27
! 2
! 2
| 28
| 28
| [[#TWI|TWI_CLK]]
| [[#TWI|I2C_2_CLK]]
|-
|-
| [[#USB Host|HOST_USB_M]]
| [[#USB Host|HOST_USB_M]]
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!
!
| 30
| 30
| [[#TWI|TWI_DAT]]
| [[#TWI|I2C_2_DAT]]
|-
|-
| [[#USB|HOST_USB_P]]
| [[#USB|HOST_USB_P]]
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!
!
| 32
| 32
| [[#GPIO|MFP_104]]
| NC
|-
|-
| CPU_CORE <ref>This pin is used as a test point to verify the CPU has a correct voltage for debugging</ref>
| 1.2V
| 33
| 33
! C
! C
| 34
| 34
| [[#I2S AuGPIO|AUD_MCLK]]
| NC
|-
|-
| [[#USB OTG|USB_OTG_M]]
| [[#USB OTG|USB_OTG_M]]
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! N
! N
| 36
| 36
| [[#I2S AuGPIO|AUD_CLK]]
| [[#I2S Audio|AUD_CLK]]
|-
|-
| [[#USB OTG|USB_OTG_P]]
| [[#USB OTG|USB_OTG_P]]
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! 2
! 2
| 38
| 38
| [[#I2S AuGPIO|AUD_FRM]]
| [[#I2S Audio|AUD_FRM]]
|-
|-
| 3.3V <ref name=power-threethree />
| 3.3V <ref name=power-threethree />
Line 438: Line 438:
!
!
| 40
| 40
| [[#I2S AuGPIO|AUD_TXD]]
| [[#I2S Audio|AUD_TXD]]
|-
|-
| Reserved
| [[#LVDS|LVDS_CLK_M]]
| 41
| 41
!
!
| 42
| 42
| [[#I2S AuGPIO|AUD_RXD]]
| [[#I2S Audio|AUD_RXD]]
|-
|-
| Reserved
| [[#LVDS|LVDS_CLK_P]]
| 43
| 43
! C
! C
| 44
| 44
| CPU_JTAG_TMS <ref name=cpujtag>Most TS-SOCKET systems run Linux, in which case the CPU JTAG bus is not useful and should not be connected. For developers who want to use another operating system, or write "bare-metal" microcontroller-style code, this CPU JTAG debugging interface is made available. If you need to use this interface, please contact Technologic Systems to order a TS-8200 base board with the CPU JTAG connector.</ref>
| Ground
|-
|-
| Ground
| Ground
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! N
! N
| 46
| 46
| CPU_JTAG_TCK <ref name=cpujtag />
| [[#LVDS|LVDS_TX1_M]]
|-
|-
| [[#PCIe|PCIE_TX-]] <ref name=pcie>PCIe is only present on the TS-4710-1066</ref>
| [[#PCIe|PCIE_TX-]]
| 47
| 47
! 2
! 2
| 48
| 48
| CPU_JTAG_TDI <ref name=cpujtag />
| [[#LVDS|LVDS_TX1_P]]
|-
|-
| [[#PCIe|PCIE_TX+]] <ref name=pcie />
| [[#PCIe|PCIE_TX+]]  
| 49
| 49
!
!
| 50
| 50
| CPU_JTAG_TDO <ref name=cpujtag />
| Ground
|-
|-
| Ground
| Ground
Line 474: Line 474:
!
!
| 52
| 52
| [[#GPIO|ONE_WIRE/MFP_84]]
| [[#GPIO|CSI0_DAT12]]
|-
|-
| [[#PCIe|PCIE_RX-]] <ref name=pcie />
| [[#PCIe|PCIE_RX-]]  
| 53
| 53
! C
! C
| 54
| 54
| [[#GPIO|MFP_51]]
| [[#I2S Audio|AUD_MCLK]]
|-
|-
| [[#PCIe|PCIE_RX+]] <ref name=pcie />
| [[#PCIe|PCIE_RX+]]  
| 55
| 55
! N
! N
| 56
| 56
| [[#Camera Interface|CAM_MCLK]]
| [[#GPIO|GPIO_5]]
|-
|-
| DDR_1.8V <ref>This pin is used as a test point to verify the RAM has a correct voltage for debugging</ref>
| DDR_1.5V <ref>This pin is used as a test point to verify the RAM has a correct voltage for debugging</ref>
| 57
| 57
! 2
! 2
| 58
| 58
| [[#Camera Interface|CAM_D0]]
| [[#GPIO|GPIO_6]]
|-
|-
| Reserved
| [[#PCIe|PCIE_CLK_P]]
| 59
| 59
!
!
| 60
| 60
| [[#Camera Interface|CAM_D1]]
| [[#FPGA|CN2-60]]
|-
|-
| Reserved
| [[#PCIe|PCIE_CLK_M]]
| 61
| 61
!
!
| 62
| 62
| [[#Camera Interface|CAM_D2]]
| [[#GPIO|GPIO_16]]
|-
|-
| AVDD_OSC <ref>This pin is used as a test point for debugging</ref>
| 1.8V <ref>This pin is used as a test point for debugging</ref>
| 63
| 63
! C
! C
| 64
| 64
| [[#Camera Interface|CAM_D5]]
| [[#GPIO|GPIO_17]]
|-
|-
| [[#SPI|SPI_FRM]]
| [[#SPI|SPI_2_CS#]]
| 65
| 65
! N
! N
| 66
| 66
| [[#Camera Interface|CAM_D6]]
| [[#GPIO|CSI0_DAT13]]
|-
|-
| [[#SPI|SPI_MOSI]]
| [[#SPI|SPI_2_MOSI]]
| 67
| 67
! 2
! 2
| 68
| 68
| [[#Camera Interface|CAM_D7]]
| [[#GPIO|GPIO_19]]
|-
|-
| [[#SPI|SPI_MISO]]
| [[#SPI|SPI_2_MISO]]
| 69
| 69
!
!
| 70
| 70
| [[#Camera Interface|CAM_HSYNC]]
| [[#GPIO|CSI0_MCLK]]
|-
|-
| [[#SPI|SPI_CLK]]
| [[#SPI|SPI_2_CLK]]
| 71
| 71
!
!
| 72
| 72
| [[#Camera Interface|CAM_VSYNC]]
| [[#GPIO|GPIO_17]]
|-
|-
| Ground
| Ground
Line 542: Line 542:
| [[#USB OTG|USB_OTG_ID]]
| [[#USB OTG|USB_OTG_ID]]
|-
|-
| Reserved
| [[#SATA|SATA_RX_M]]
| 75
| 75
! N
! N
| 76
| 76
| USB_5V_LINE <ref>This should be supplied with 5V to power the USB ports.</ref>
| [[#USB_OTG|USB_OTG_VBUS]]
|-
|-
| Reserved
| [[#SATA|SATA_RX_P]]
| 77
| 77
! 2
! 2
| 78
| 78
| [[#GPIO|GPIO_48]] / [[#XUARTS|UART0_TXD]]
| [[#FPGA|CN2-78]] / [[#COM Ports|ttymxc1 txd]]
|-
|-
| [[#CPU JTAG|CPU_JTAG_VCC]]
| 3.3V
| 79
| 79
!
!
| 80
| 80
| [[#GPIO|GPIO_49]] / [[#XUARTS|UART0_RXD]]
| [[#FPGA|CN2-80]] / [[#COM Ports|ttymxc1 rxd]]
|-
|-
| [[#Camera Interface|CAM_D3]]
| [[#SATA|SATA_TX_M]]
| 81
| 81
!
!
| 82
| 82
| [[#GPIO|GPIO_50]] / [[#XUARTS|UART1_TXD]]
| [[#FPGA|CN2-82]] / [[#COM Ports|ttymxc2 txd]]
|-
|-
| [[#Camera Interface|CAM_D4]]
| [[#SATA|SATA_TX_P]]
| 83
| 83
! C
! C
| 84
| 84
| [[#GPIO|GPIO_51]] / [[#XUARTS|UART1_RXD]]
| [[#FPGA|CN2-84]] / [[#COM Ports|ttymxc2 rxd]]
|-
|-
| [[#Camera Interface|CAM_PCLK]]
| Ground
| 85
| 85
! N
! N
| 86
| 86
| [[#GPIO|GPIO_52]] / [[#XUARTS|UART2_TXD]]
| [[#FPGA|CN2-86]] / [[#COM Ports|ttymxc3 txd]]
|-
|-
| [[#Camera Interface|CAM_VCLK]]
| NC
| 87
| 87
! 2
! 2
| 88
| 88
| [[#GPIO|GPIO_53]] / [[#XUARTS|UART2_RXD]]
| [[#FPGA|CN2-88]] / [[#COM Ports|ttymxc3 rxd]]
|-
|-
| [[#GPIO|MFP_52]]
| NC
| 89
| 89
!
!
| 90
| 90
| [[#GPIO|GPIO_54]] / [[#XUARTS|UART3_TXD]]
| [[#FPGA|CN2-90]] / [[#COM Ports|ttymxc4 txd]]
|-
|-
| [[#GPIO|MFP_43]]
| NC
| 91
| 91
!
!
| 92
| 92
| [[#GPIO|GPIO_55]] / [[#XUARTS|UART3_RXD]]
| [[#FPGA|CN2-92]] / [[#COM Ports|ttymxc4 rxd]]
|-
|-
| [[#Get a console|DEBUG_TXD]]
| [[#Get a console|DEBUG_TXD]]
Line 600: Line 600:
! C
! C
| 94
| 94
| [[#GPIO|GPIO_56]] / [[#XUARTS|UART4_TXD]]
| [[#FPGA|CN2-94]]
|-
|-
| [[#Get a console|DEBUG_RXD]]
| [[#Get a console|DEBUG_RXD]]
Line 606: Line 606:
! N
! N
| 96
| 96
| [[#GPIO|GPIO_57]] / [[#XUARTS|UART4_RXD]]
| [[#FPGA|CN2-96]]
|-
|-
| [[#GPIO|GPIO_15]] / [[#CAN|CAN_TXD]]
| [[#CAN|CAN_1_TXD]]
| 97
| 97
! 2
! 2
| 98
| 98
| [[#GPIO|GPIO_58]] / [[#XUARTS|UART5_TXD]]
| [[#FPGA|CN2-98]]
|-
|-
| [[#GPIO|GPIO_16]] / [[#CAN|CAN1 RXD]]
| [[#CAN|CAN_1_RXD]]
| 99
| 99
!
!
| 100
| 100
| [[#GPIO|GPIO_59]] / [[#XUARTS|UART5_RXD]]
| [[#FPGA|CN2-100]]
|}
|}
|}
|}


<references />
<references />

Revision as of 17:44, 5 September 2014

CN1 CN2
Name Pin Pin Name
NC 1 2 EXT_RESET# [1]
NC 3 C 4 EN_USB_5V [2]
NC 5 N 6 SD2_D2 [3]
NC 7 1 8 SD2_D3 [3]
OFF_BD_RESET# [4] 9 10 SD2_CMD [3]
NC 11 12 3.3V
NC 13 C 14 SD2_CLK [3]
5V [5] 15 N 16 5V [5]
NC 17 1 18 SD2_D0 [3]
LCD_D08 19 20 SD2_D1 [3]
LCD_D09 21 22 NC
LCD_D10 23 C 24 LCD_D00
LCD_D11 25 N 26 LCD_D01
LCD_D12 27 1 28 LCD_D02
5V [5] 29 30 LCD_D03
LCD_D13 31 32 LCD_D04
LCD_D14 33 C 34 LCD_D05
LCD_D15 35 N 36 V_BAT
LCD_D16 37 1 38 LCD_D06
LCD_D17 39 40 LCD_D07
LCD_D18 41 42 LCD_D21
LCD_D19 43 C 44 LCD_D22
LCD_D20 45 N 46 LCD_D23
5V [5] 47 1 48 EN_LCD_3.3V
LCD_CLK 49 50 NC
LCD_HSYNC 51 52 BOOT_MODE_0
LCD_VSYNC 53 C 54 BOOT_MODE_1
LCD_DE 55 N 56 SPI_1_MISO
LCD_PWM 57 1 58 SPI_1_MOSI
SPI_FLASH_CS# [6] 59 60 SPI_1_CLK
SPI_1_CS1# 61 62 Ground
CN1-63 / ttymxc3 TXEN 63 C 64 EIM_DA15 / MUX_AD_15
EIM_EB1 65 N 66 EIM_DA14 / MUX_AD_14
CN1-67 / ttymxc1 TXEN 67 1 68 EIM_DA13 / MUX_AD_13
CAN2_RXD 69 70 EIM_DA12 / MUX_AD_12
CAN2_TXD 71 72 EIM_DA11 / MUX_AD_11
PUSH_SW# 73 C 74 EIM_DA10 / MUX_AD_10
Ground 75 N 76 EIM_DA09 / MUX_AD_09
EIM_A21 77 1 78 EIM_DA08 / MUX_AD_08
EIM_BCLK 79 80 EIM_DA07 / MUX_AD_07
EIM_A18 81 82 EIM_DA06 / MUX_AD_06
EIM_OE 83 C 84 EIM_DA05 / MUX_AD_05
EIM_A20 85 N 86 EIM_DA04 / MUX_AD_04
CN1-87 / #Offboard Clock 87 1 88 EIM_DA03 / MUX_AD_03
EIM_A22 / Offboard IRQ 69 89 90 EIM_DA02 / MUX_AD_02
EIM_A23 91 92 EIM_DA03 / MUX_AD_01
EIM_A24 93 C 94 EIM_DA00 / MUX_AD_00
Ground 95 N 96 EIM_LBA / BUS_ALE#
EIM_WAIT / BUS_WAIT# 97 1 98 EIM_RW / SDBOOT / BUS_DIR
EIM_D31 / BUS_BHE# 99 100 EIM_CS0 /BUS_CS#
Name Pin Pin Name
MDI_0_P 1 2 ETH_ACT_LED
MDI_0_M 3 C 4 ETH_LINK_LED
ETH_CT 5 N 6 RED_LED#
MDI_1_P 7 2 8 GREEN_LED#
MDI_1_M 9 10 LVDS_TX3_P
ETH_CT 11 12 LVDS_TX3_N
3.3V [7] 13 C 14 Ground
Ground 15 N 16 LVDS_TX2_P
MDI_2_P 17 2 18 LVDS_TX2_P
MDI_2_N 19 20 NC
Ground 21 22 LVDS_TX0_P
MDI_3_P 23 C 24 NC
MDI_3_N 25 N 26 NC
1.2V 27 2 28 I2C_2_CLK
HOST_USB_M 29 30 I2C_2_DAT
HOST_USB_P 31 32 NC
1.2V 33 C 34 NC
USB_OTG_M 35 N 36 AUD_CLK
USB_OTG_P 37 2 38 AUD_FRM
3.3V [7] 39 40 AUD_TXD
LVDS_CLK_M 41 42 AUD_RXD
LVDS_CLK_P 43 C 44 Ground
Ground 45 N 46 LVDS_TX1_M
PCIE_TX- 47 2 48 LVDS_TX1_P
PCIE_TX+ 49 50 Ground
Ground 51 52 CSI0_DAT12
PCIE_RX- 53 C 54 AUD_MCLK
PCIE_RX+ 55 N 56 GPIO_5
DDR_1.5V [8] 57 2 58 GPIO_6
PCIE_CLK_P 59 60 CN2-60
PCIE_CLK_M 61 62 GPIO_16
1.8V [9] 63 C 64 GPIO_17
SPI_2_CS# 65 N 66 CSI0_DAT13
SPI_2_MOSI 67 2 68 GPIO_19
SPI_2_MISO 69 70 CSI0_MCLK
SPI_2_CLK 71 72 GPIO_17
Ground 73 C 74 USB_OTG_ID
SATA_RX_M 75 N 76 USB_OTG_VBUS
SATA_RX_P 77 2 78 CN2-78 / ttymxc1 txd
3.3V 79 80 CN2-80 / ttymxc1 rxd
SATA_TX_M 81 82 CN2-82 / ttymxc2 txd
SATA_TX_P 83 C 84 CN2-84 / ttymxc2 rxd
Ground 85 N 86 CN2-86 / ttymxc3 txd
NC 87 2 88 CN2-88 / ttymxc3 rxd
NC 89 90 CN2-90 / ttymxc4 txd
NC 91 92 CN2-92 / ttymxc4 rxd
DEBUG_TXD 93 C 94 CN2-94
DEBUG_RXD 95 N 96 CN2-96
CAN_1_TXD 97 2 98 CN2-98
CAN_1_RXD 99 100 CN2-100
  1. ↑ EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
  2. ↑ This is an output which can be manipulated in the #Syscon. This pin can optionally be connected to control a FET to a separate 5V rail for USB to allow software to reset USB devices.
  3. ↑ 3.0 3.1 3.2 3.3 3.4 3.5 This SD interface is the same one used by the MicroSD on the TS-4900. Only one can be used at a time.
  4. ↑ OFF_BD_RESET# is an output from the macrocontroller that automatically sends a reset signal when the unit powers up or reboots. It can be connected to any IC on the base board that requires a reset.
  5. ↑ 5.0 5.1 5.2 5.3 The 5V power pins should each be connected to a 5V source.
  6. ↑ This is used during production to boot to an offboard SPI flash. This pin should typically be left unconnected.
  7. ↑ 7.0 7.1 The TS-4900 regulates a 3.3V rail which can source up to 700mA. Designs should target a 300mA max if they intend to use other macrocontrollers.
  8. ↑ This pin is used as a test point to verify the RAM has a correct voltage for debugging
  9. ↑ This pin is used as a test point for debugging
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