4300 TS-Socket: Difference between revisions

From embeddedTS Manuals
(Created page with "{| ! CN1 ! CN2 |- | {| class=wikitable ! Name ! Pin ! ! Pin ! Name |- | FPGA_JTAG_TMS <ref name=FPGAJTAG>The FPGA JTAG pins are not recommended for use and are not supported....")
 
No edit summary
Line 201: Line 201:
! C
! C
| 64
| 64
| [[#DIO|DIO_74]] / [[#MUXBUS|AD_15]]
| [[#DIO|DIO_89]] / [[#MUXBUS|AD_15]]
|-
|-
| [[#DIO|DIO_13]]
| [[#DIO|DIO_13]]
Line 207: Line 207:
! N
! N
| 66
| 66
| [[#DIO|DIO_33]] / [[#MUXBUS|AD_14]]
| [[#DIO|DIO_88]] / [[#MUXBUS|AD_14]]
|-
|-
| [[#DIO|DIO_12]]
| [[#DIO|DIO_12]]
Line 213: Line 213:
! 1
! 1
| 68
| 68
| [[#DIO|DIO_32]] / [[#MUXBUS|AD_13]]
| [[#DIO|DIO_87]] / [[#MUXBUS|AD_13]]
|-
|-
| [[#DIO|DIO_11]]
| [[#DIO|DIO_11]]
Line 219: Line 219:
!
!
| 70
| 70
| [[#DIO|DIO_31]] / [[#MUXBUS|AD_12]]
| [[#DIO|DIO_86]] / [[#MUXBUS|AD_12]]
|-
|-
| [[#DIO|DIO_10]]
| [[#DIO|DIO_10]]
Line 225: Line 225:
!
!
| 72
| 72
| [[#DIO|DIO_30]] / [[#MUXBUS|AD_11]]
| [[#DIO|DIO_85]] / [[#MUXBUS|AD_11]]
|-
|-
| [[#DIO|DIO_09]]
| [[#DIO|DIO_09]]
Line 231: Line 231:
! C
! C
| 74
| 74
| [[#DIO|DIO_29]] / [[#MUXBUS|AD_10]]
| [[#DIO|DIO_84]] / [[#MUXBUS|AD_10]]
|-
|-
| Ground
| Ground
Line 237: Line 237:
! N
! N
| 76
| 76
| [[#DIO|DIO_28]] / [[#MUXBUS|AD_09]]
| [[#DIO|DIO_83]] / [[#MUXBUS|AD_09]]
|-
|-
| [[#DIO|DIO_08]]
| [[#DIO|DIO_08]]
Line 243: Line 243:
! 1
! 1
| 78
| 78
| [[#DIO|DIO_27]] / [[#MUXBUS|AD_08]]
| [[#DIO|DIO_82]] / [[#MUXBUS|AD_08]]
|-
|-
| [[#DIO|DIO_07]]
| [[#DIO|DIO_07]]
Line 249: Line 249:
!
!
| 80
| 80
| NAND_D7 / [[#MUXBUS|AD_07]]
| [[#DIO|DIO_81]] / [[#MUXBUS|AD_07]]
|-
|-
| [[#DIO|DIO_06]]
| [[#DIO|DIO_06]]
Line 255: Line 255:
!
!
| 82
| 82
| NAND_D6 / [[#MUXBUS|AD_06]]
| [[#DIO|DIO_80]] / [[#MUXBUS|AD_06]]
|-
|-
| [[#DIO|DIO_05]]
| [[#DIO|DIO_05]]
Line 261: Line 261:
! C
! C
| 84
| 84
| NAND_D5 / [[#MUXBUS|AD_05]]
| [[#DIO|DIO_79]] / [[#MUXBUS|AD_05]]
|-
|-
| [[#DIO|DIO_04]]
| [[#DIO|DIO_04]]
Line 267: Line 267:
! N
! N
| 86
| 86
| NAND_D4 / [[#MUXBUS|AD_04]]
| [[#DIO|DIO_78]] / [[#MUXBUS|AD_04]]
|-
|-
| [[#DIO|DIO_03]]
| [[#DIO|DIO_03]]
Line 273: Line 273:
! 1
! 1
| 88
| 88
| NAND_D3 / [[#MUXBUS|AD_03]]
| [[#DIO|DIO_77]] / [[#MUXBUS|AD_03]]
|-
|-
| [[#DIO|DIO_02]]
| [[#DIO|DIO_02]]
Line 279: Line 279:
!
!
| 90
| 90
| NAND_D2 / [[#MUXBUS|AD_02]]
| [[#DIO|DIO_76]] / [[#MUXBUS|AD_02]]
|-
|-
| [[#DIO|DIO_01]]
| [[#DIO|DIO_01]]
Line 285: Line 285:
!
!
| 92
| 92
| NAND_D1 / [[#MUXBUS|AD_01]]
| [[#DIO|DIO_75]] / [[#MUXBUS|AD_01]]
|-
|-
| [[#DIO|DIO_00]]
| [[#DIO|DIO_00]]
Line 291: Line 291:
! C
! C
| 94
| 94
| NAND_D0 / [[#MUXBUS|AD_00]]
| [[#DIO|DIO_74]] / [[#MUXBUS|AD_00]]
|-
|-
| Ground
| Ground
Line 297: Line 297:
! N
! N
| 96
| 96
| [[#DIO|DIO_26]] / [[#MUXBUS|BUS_ALE#]]
| [[#DIO|DIO_94]] / [[#MUXBUS|BUS_ALE#]]
|-
|-
| Reserved
| [[#DIO|DIO_90]] / [[#MUXBUS|BUS_WAIT#]]
| 97
| 97
! 1
! 1
| 98
| 98
| [[#DIO|DIO_25]] / [[#MUXBUS|BUS_DIR]]
| [[#DIO|DIO_93]] / [[#MUXBUS|BUS_DIR]]
|-
|-
| [[#DIO|DIO_23]] / [[#MUXBUS|BUS_BHE#]]
| [[#DIO|DIO_91]] / [[#MUXBUS|BUS_BHE#]]
| 99
| 99
!
!
| 100
| 100
| [[#DIO|DIO_24]] / [[#MUXBUS|BUS_CS#]]
| [[#DIO|DIO_92]] / [[#MUXBUS|BUS_CS#]]
|}
|}


Line 336: Line 336:
! N
! N
| 6
| 6
| [[#LED|RED_LED#]]
| [[#Syscon|RED_LED#]]
|-
|-
| [[#Ethernet Port|ETH_TX+]]
| [[#Ethernet Port|ETH_TX+]]
Line 342: Line 342:
! 2
! 2
| 8
| 8
| [[#LED|GREEN_LED#]]
| [[#Syscon|GREEN_LED#]]
|-
|-
| [[#Ethernet Port|ETH_TX-]]
| [[#Ethernet Port|ETH_TX-]]
Line 348: Line 348:
!
!
| 10
| 10
| Reserved
| [[#DIO|GPIO_A31]]
|-
|-
| [[#Ethernet Port|ETH_CT]]
| [[#Ethernet Port|ETH_CT]]
Line 354: Line 354:
!
!
| 12
| 12
| Reserved
| [[#DIO|GPIO_B0]]
|-
|-
| 3.3V <ref name=33RAIL>The macrocontroller regulates a 3.3V rail which can source up to 300mA by the baseboard.</ref>
| 3.3V <ref name=33RAIL>The macrocontroller regulates a 3.3V rail which can source up to 700mA by the baseboard.</ref>
| 13
| 13
! C
! C
Line 386: Line 386:
| Reserved
| Reserved
|-
|-
| [[#USB Device|DEV_USB_M]]
| Reserved
| 23
| 23
! C
! C
Line 392: Line 392:
| Reserved
| Reserved
|-
|-
| [[#USB Device|DEV_USB_P]]
| Reserved
| 25
| 25
! N
! N
Line 414: Line 414:
!
!
| 32
| 32
| Reserved
| [[#DIO|GPIO_B17]]
|-
|-
| CPU_CORE
| CPU_CORE
Line 420: Line 420:
! C
! C
| 34
| 34
| Reserved
| AUD_MCLK
|-
|-
| [[#USB Host|HOSTB_USB_M]]
| [[#USB OTG|USB_OTG_M]]
| 35
| 35
! N
! N
| 36
| 36
| Reserved
| [[#DIO|GPIO_B22]]
|-
|-
| [[#USB Host|HOSTB_USB_P]]
| [[#USB OTG|USB_OTG_P]]
| 37
| 37
! 2
! 2
| 38
| 38
| Reserved
| [[#DIO|GPIO_B23]]
|-
|-
| 3.3V <ref name=33RAIL />
| 3.3V <ref name=33RAIL />
Line 438: Line 438:
!
!
| 40
| 40
| Reserved
| [[#DIO|GPIO_B24]]
|-
|-
| Reserved
| Reserved
Line 444: Line 444:
!
!
| 42
| 42
| Reserved
| [[#DIO|GPIO_B25]]
|-
|-
| Reserved
| Reserved
Line 458: Line 458:
| CPU_JTAG_TCK
| CPU_JTAG_TCK
|-
|-
| Reserved
| CPU_PCIE_TX1_M
| 47
| 47
! 2
! 2
Line 464: Line 464:
| CPU_JTAG_TDI
| CPU_JTAG_TDI
|-
|-
| Reserved
| CPU_PCIE_TX1_P
| 49
| 49
!
!
Line 470: Line 470:
| CPU_JTAG_TDO
| CPU_JTAG_TDO
|-
|-
| | Ground
| Ground
| 51
| 51
!
!
| 52
| 52
| Reserved
| [[#DIO|DIO_73]]
|-
|-
| Reserved
| Reserved
| 53
| CPU_PCIE_RX1_M
! C
! C
| 54
| 54
| [[#DIO|DIO_50]]
| [[#DIO|DIO_72]]
|-
|-
| Reserved
| CPU_PCIE_RX1_P
| 55
| 55
! N
! N
| 56
| 56
| [[#DIO|DIO_51]]
| [[#DIO|DIO_71]]
|-
|-
| 1.8V
| DDR 1.8V <ref>Maximum off-board load on DDR_1.8V is 100mA</ref>
| 57
| 57
! 2
! 2
| 58
| 58
| [[#DIO|DIO_52]]
| [[#DIO|DIO_70]]
|-
|-
| Reserved
| PCIE_CLK3_M
| 59
| 59
!
!
| 60
| 60
| [[#DIO|DIO_43]]
| [[#DIO|DIO_69]]
|-
|-
| Reserved
| PCIE_CLK3_P
| 61
| 61
!
!
| 62
| 62
| [[#DIO|DIO_49]]
| [[#DIO|DIO_68]]
|-
|-
| 1.2V
| 2.5V <ref>Maximum off-board load on 2.5V is 10mA</ref>
| 63
| 63
! C
! C
| 64
| 64
| [[#DIO|DIO_17]]
| [[#DIO|DIO_67]]
|-
|-
| [[#DIO|DIO_48]]
| [[#SPI|SPI_CS]]
| 65
| 65
! N
! N
| 66
| 66
| [[#DIO|DIO_18]]
| [[#DIO|DIO_66]]
|-
|-
| [[#SPI|SPI_MOSI]]
| [[#SPI|SPI_MOSI]]
Line 522: Line 522:
! 2
! 2
| 68
| 68
| [[#DIO|DIO_19]]
| [[#DIO|DIO_65]]
|-
|-
| [[#SPI|SPI_MISO]]
| [[#SPI|SPI_MISO]]
Line 528: Line 528:
!
!
| 70
| 70
| [[#DIO|DIO_20]]
| [[#DIO|DIO_64]]
|-
|-
| [[#SPI|SPI_CLK]]
| [[#SPI|SPI_CLK]]
Line 534: Line 534:
!
!
| 72
| 72
| [[#DIO|DIO_21]]
| [[#DIO|DIO_63]]
|-
|-
| Ground
| Ground
Line 540: Line 540:
! C
! C
| 74
| 74
| Reserved
| [[#USB OTG|USB_OTG_ID]]
|-
|-
| Reserved
| Reserved
Line 546: Line 546:
! N
! N
| 76
| 76
| Reserved
| [[#USB OTG|USB_OTG_5V]]
|-
|-
| Reserved
| Reserved
Line 552: Line 552:
! 2
! 2
| 78
| 78
| [[#DIO|DIO_36]] / [[#COM Ports|XUART0_TXD]]
| [[#DIO|DIO_96]] / [[#COM Ports|XUART0_TXD]]
|-
|-
| 3.3V <ref name=33RAIL />
| 3.3V <ref name=33RAIL />
Line 558: Line 558:
!
!
| 80
| 80
| [[#DIO|DIO_37]] / [[#COM Ports|UART0_RXD]]
| [[#DIO|DIO_97]] / [[#COM Ports|UART0_RXD]]
|-
|-
| Reserved
| Reserved
Line 564: Line 564:
!
!
| 82
| 82
| [[#DIO|DIO_38]] / [[#COM Ports|UART1_TXD]]
| [[#DIO|DIO_98]] / [[#COM Ports|UART1_TXD]]
|-
|-
| Reserved
| Reserved
Line 570: Line 570:
! C
! C
| 84
| 84
| | [[#DIO|DIO_39]] / [[#COM Ports|UART1_RXD]]
| [[#DIO|DIO_99]] / [[#COM Ports|UART1_RXD]]
|-
|-
| Reserved
| Reserved
Line 576: Line 576:
! N
! N
| 86
| 86
| [[#DIO|DIO_22]] / [[#COM Ports|UART2_TXD]]
| [[#DIO|DIO_100]] / [[#COM Ports|UART2_TXD]]
|-
|-
| Reserved
| Reserved
Line 582: Line 582:
! 2
! 2
| 88
| 88
| [[#DIO|DIO_44]] / [[#COM Ports|UART2_RXD]]
| [[#DIO|DIO_101]] / [[#COM Ports|UART2_RXD]]
|-
|-
| Reserved
| Reserved
Line 588: Line 588:
!
!
| 90
| 90
| [[#DIO|DIO_45]] / [[#COM Ports|UART3_TXD]]
| [[#DIO|DIO_102]] / [[#COM Ports|UART3_TXD]]
|-
|-
| Reserved
| Reserved
Line 594: Line 594:
!
!
| 92
| 92
| [[#DIO|DIO_46]] / [[#COM Ports|UART3_RXD]]
| [[#DIO|DIO_103]] / [[#COM Ports|UART3_RXD]]
|-
|-
| [[#Debug Console|DEBUG_TXD]]
| [[#Get a Console|DEBUG_TXD]]
| 93
| 93
! C
! C
| 94
| 94
| [[#DIO|DIO_47]] / [[#COM Ports|UART4_TXD]]
| [[#DIO|DIO_104]] / [[#COM Ports|UART4_TXD]]
|-
|-
| [[#Debug Console|DEBUG_RXD]]
| [[#Get a Console|DEBUG_RXD]]
| 95
| 95
! N
! N
| 96
| 96
| | [[#DIO|DIO_40]] / [[#COM Ports|UART4_RXD]]
| [[#DIO|DIO_105]] / [[#COM Ports|UART4_RXD]]
|-
|-
| [[#DIO|DIO_15]] / [[#CAN|CAN_TXD]]
| [[#DIO|DIO_15]] / [[#CAN|CAN_TXD]]
Line 612: Line 612:
! 2
! 2
| 98
| 98
| [[#DIO|DIO_41]] / [[#COM Ports|UART5_TXD]]
| [[#DIO|DIO_106]] / [[#COM Ports|UART5_TXD]]
|-
|-
| [[#DIO|DIO_16]] / [[#CAN|CAN_RXD]]
| [[#DIO|DIO_16]] / [[#CAN|CAN_RXD]]
Line 618: Line 618:
!
!
| 100
| 100
| [[#DIO|DIO_42]] / [[#COM Ports|UART5_RXD]]
| [[#DIO|DIO_107]] / [[#COM Ports|UART5_RXD]]
|}
|}
|}
|}


<references />
<references />

Revision as of 18:00, 6 December 2012

CN1 CN2
Name Pin Pin Name
FPGA_JTAG_TMS [1] 1 2 #EXT_RESET [2]
FPGA_JTAG_TCK [1] 3 C 4 EN_USB_5V [3]
FPGA_JTAG_TDO [1] 5 N 6 DIO_62
FPGA_JTAG_TDI [1] 7 1 8 DIO_61
OFF_BD_RESET# [4] 9 10 DIO_60
DIO_17 11 12 DIO_59
DIO_18 13 C 14 DIO_58
POWER [5] 15 N 16 POWER [5]
DIO_37 17 1 18 DIO_57
DIO_36 19 20 DIO_56
DIO_35 21 22 DIO_55
DIO_34 23 C 24 DIO_54
DIO_33 25 N 26 DIO_53
DIO_32 27 1 28 DIO_52
POWER [5] 29 30 DIO_51
DIO_31 31 32 DIO_50
DIO_30 33 C 34 DIO_49
DIO_29 35 N 36 V_BAT [6]
DIO_28 37 1 38 DIO_48
DIO_27 39 40 DIO_47
DIO_26 41 42 DIO_46
DIO_25 43 C 44 DIO_45
DIO_24 45 N 46 DIO_44
POWER [5] 47 1 48 EN_LCD_3.3V [7]
DIO_23 49 50 DIO_43
DIO_22 51 52 DIO_42
DIO_21 53 C 54 DIO_41
DIO_20 55 N 56 FLASH_DOUT [8]
DIO_19 57 1 58 FLASH_DIN [8]
FLASH_CS# [8] 59 60 FLASH_CLK [8]
FPGA_FLASH_CS# [8] 61 62 Ground
DIO_14 63 C 64 DIO_89 / AD_15
DIO_13 65 N 66 DIO_88 / AD_14
DIO_12 67 1 68 DIO_87 / AD_13
DIO_11 69 70 DIO_86 / AD_12
DIO_10 71 72 DIO_85 / AD_11
DIO_09 73 C 74 DIO_84 / AD_10
Ground 75 N 76 DIO_83 / AD_09
DIO_08 77 1 78 DIO_82 / AD_08
DIO_07 79 80 DIO_81 / AD_07
DIO_06 81 82 DIO_80 / AD_06
DIO_05 83 C 84 DIO_79 / AD_05
DIO_04 85 N 86 DIO_78 / AD_04
DIO_03 87 1 88 DIO_77 / AD_03
DIO_02 89 90 DIO_76 / AD_02
DIO_01 91 92 DIO_75 / AD_01
DIO_00 93 C 94 DIO_74 / AD_00
Ground 95 N 96 DIO_94 / BUS_ALE#
DIO_90 / BUS_WAIT# 97 1 98 DIO_93 / BUS_DIR
DIO_91 / BUS_BHE# 99 100 DIO_92 / BUS_CS#
Name Pin Pin Name
ETH_RX+ 1 2 ETH_LEFT_LED
ETH_RX- 3 C 4 ETH_RIGHT_LED
ETH_CT 5 N 6 RED_LED#
ETH_TX+ 7 2 8 GREEN_LED#
ETH_TX- 9 10 GPIO_A31
ETH_CT 11 12 GPIO_B0
3.3V [9] 13 C 14 Reserved
Ground 15 N 16 Reserved
Reserved 17 2 18 Reserved
Reserved 19 20 Reserved
Ground 21 22 Reserved
Reserved 23 C 24 Reserved
Reserved 25 N 26 Reserved
Ground 27 2 28 TWI_CLK
HOST_USB_M 29 30 TWI_DAT
HOST_USB_P 31 32 GPIO_B17
CPU_CORE 33 C 34 AUD_MCLK
USB_OTG_M 35 N 36 GPIO_B22
USB_OTG_P 37 2 38 GPIO_B23
3.3V [9] 39 40 GPIO_B24
Reserved 41 42 GPIO_B25
Reserved 43 C 44 CPU_JTAG_TMS
Ground 45 N 46 CPU_JTAG_TCK
CPU_PCIE_TX1_M 47 2 48 CPU_JTAG_TDI
CPU_PCIE_TX1_P 49 50 CPU_JTAG_TDO
Ground 51 52 DIO_73
Reserved CPU_PCIE_RX1_M C 54 DIO_72
CPU_PCIE_RX1_P 55 N 56 DIO_71
DDR 1.8V [10] 57 2 58 DIO_70
PCIE_CLK3_M 59 60 DIO_69
PCIE_CLK3_P 61 62 DIO_68
2.5V [11] 63 C 64 DIO_67
SPI_CS 65 N 66 DIO_66
SPI_MOSI 67 2 68 DIO_65
SPI_MISO 69 70 DIO_64
SPI_CLK 71 72 DIO_63
Ground 73 C 74 USB_OTG_ID
Reserved 75 N 76 USB_OTG_5V
Reserved 77 2 78 DIO_96 / XUART0_TXD
3.3V [9] 79 80 DIO_97 / UART0_RXD
Reserved 81 82 DIO_98 / UART1_TXD
Reserved 83 C 84 DIO_99 / UART1_RXD
Reserved 85 N 86 DIO_100 / UART2_TXD
Reserved 87 2 88 DIO_101 / UART2_RXD
Reserved 89 90 DIO_102 / UART3_TXD
Reserved 91 92 DIO_103 / UART3_RXD
DEBUG_TXD 93 C 94 DIO_104 / UART4_TXD
DEBUG_RXD 95 N 96 DIO_105 / UART4_RXD
DIO_15 / CAN_TXD 97 2 98 DIO_106 / UART5_TXD
DIO_16 / CAN_RXD 99 100 DIO_107 / UART5_RXD
  1. ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported. See the #FPGA Programming section for the recommended method to reprogram the FPGA.
  2. ↑ EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
  3. ↑ On our baseboard designs this pin is typically used to toggle power to the USB 5V rail.
  4. ↑ The off board reset is driven low to reset all peripherals.
  5. ↑ 5.0 5.1 5.2 5.3 Power pins all supply power to the module. Apply 4.0V to 5.5V to these pins.
  6. ↑ Optionally you can connect a 3.3V battery to this pin to keep the RTC alive between reboots and while the 5V rail is down.
  7. ↑ On our off the shelf baseboards this is used to toggle the 3.3V power supply for an LCD interface such as on the TS-8390.
  8. ↑ 8.0 8.1 8.2 8.3 8.4 These are SPI flash pins. Custom baseboard designs can contain their own supported SPI flash chip which can be used to boot, or access with spiflashctl.
  9. ↑ 9.0 9.1 9.2 The macrocontroller regulates a 3.3V rail which can source up to 700mA by the baseboard.
  10. ↑ Maximum off-board load on DDR_1.8V is 100mA
  11. ↑ Maximum off-board load on 2.5V is 10mA
Retrieved from "http://docs.embeddedTS.com/index.php?title=4300_TS-Socket&oldid=2868"