4700 FPGA Functionality: Difference between revisions
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All macrocontrollers feature an FPGA. Any external interfaces called for by the TS-SOCKET specification that are not provided by the CPU are implemented in the FPGA whenever possible. The FPGA is connected to the CPU by a static memory controller, and as a result the FPGA can provide registers in the CPU memory space. | All macrocontrollers feature an FPGA. Any external interfaces called for by the TS-SOCKET specification that are not provided by the CPU are implemented in the FPGA whenever possible. The FPGA is connected to the CPU by a static memory controller, and as a result the FPGA can provide registers in the CPU memory space. | ||
While most common functionality for the TS-4700 is accessed through layers of software that are already written, some features may require talking directly to the FPGA. The TS-4700 provides access to the FPGA in an 8 bit region and a 16 bit region. | While most common functionality for the TS-4700 is accessed through layers of software that are already written, some features may require talking directly to the FPGA. The TS-4700 provides access to the FPGA in an 8 bit region and a 16 bit region. All registers inside the TS-4700 FPGA are 16 bit registers, but both 8 bit and 16 bit reads are possible. Use the one appropriate for the hardware core you are talking to. For example, the CAN core is 8 bit, the 8 bit MUXBUS space is 8 bit, and some 8 bit cycles are needed for the SPI core if you want to do 8 bit SPI transactions. To access hardware cores in the FPGA, add the offset in the table below to the base address. | ||
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Revision as of 19:33, 29 February 2012
All macrocontrollers feature an FPGA. Any external interfaces called for by the TS-SOCKET specification that are not provided by the CPU are implemented in the FPGA whenever possible. The FPGA is connected to the CPU by a static memory controller, and as a result the FPGA can provide registers in the CPU memory space.
While most common functionality for the TS-4700 is accessed through layers of software that are already written, some features may require talking directly to the FPGA. The TS-4700 provides access to the FPGA in an 8 bit region and a 16 bit region. All registers inside the TS-4700 FPGA are 16 bit registers, but both 8 bit and 16 bit reads are possible. Use the one appropriate for the hardware core you are talking to. For example, the CAN core is 8 bit, the 8 bit MUXBUS space is 8 bit, and some 8 bit cycles are needed for the SPI core if you want to do 8 bit SPI transactions. To access hardware cores in the FPGA, add the offset in the table below to the base address.
Bit Width | Base Address |
---|---|
16 | 0x80000000 |
8 | 0x81000000 |
Offset | Usage | Bit Width |
---|---|---|
0x0000 | 16KB blockram access (for XUART buffer) | 16 |
0x4000 | Syscon registers | 16 |
0x4400 | ADC registers (for off-board ADC) | 16 |
0x4800 | SPI interface | 16 |
0x4C00 | CAN controller | 8 |
0x4D00 | 2nd CAN controller | 8 |
0x5000 | Touchscreen registers | 16 |
0x5400 | XUART IO registers | 16 |
0x8000 | 32KB MUXBUS space | 16/8 |