4700 Syscon: Difference between revisions

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m (Reverted edits by Mpeters (talk) to last revision by Mark)
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Line 13: Line 13:
| rowspan="12" | 0x02
| rowspan="12" | 0x02
| 15
| 15
| Reset switch enable (Use DIO 9 input)
| [[#DIO|Reset switch enable (Use DIO 9 input)]]
|-
|-
| 14
| 14
Line 19: Line 19:
|-
|-
| 13
| 13
| Enable UART4 TXEN (override DIO 14)
| [[#XUARTs|Enable UART4 TXEN (override DIO 14)]]
|-
|-
| 12
| 12
| Enable UART0 TXEN (override DIO 12)
| [[#XUARTs|Enable UART0 TXEN (override DIO 12)]]
|-
|-
| 11
| 11
| Enable 12.5MHz base board clock (override DIO 3)
| [[#DIO|Enable 12.5MHz base board clock (override DIO 3)]]
|-
|-
| 10
| 10
| Enable SPI (override DIO 17-20)  
| [[#SPI|Enable SPI (override DIO 17-20)]]
|-
|-
| 9
| 9
| Enable 2nd CAN (override DIO 10,11)
| [[#CAN|Enable 2nd CAN]] ([[#DIO|override DIO 10,11]])
|-
|-
| 8
| 8
| Enable CAN (override DIO 15,16)  
| [[#CAN|Enable CAN]] ([[#DIO|override DIO 15,16]])  
|-
|-
| 7:6
| 7:6
| Scratch Register (used by bootrom)
| Scratch Register
|-
|-
| 5
| 5
| Mode2
| [[#Booting_up_the_board|Mode2]]
|-
|-
| 4
| 4
| Mode1  
| [[#Booting_up_the_board|Mode1]]
|-
|-
| 3:0
| 3:0
Line 50: Line 50:
| 0x04
| 0x04
| 15:0
| 15:0
| Muxbus configuration register
| [[#MUXBUS|Muxbus configuration register]]
|-
|-
| 0x06
| 0x06
| 15:0
| 15:0
| Watchdog feed register
| [[#Watchdog|Watchdog feed register]]
|-
|-
| 0x08
| 0x08
Line 90: Line 90:
|-
|-
| 10:5
| 10:5
| DIO 26:22 output data
| [[#DIO|DIO 26:22 output data]]
|-
|-
| 4:0
| 4:0
| DIO 20:15 output data
| [[#DIO| DIO 20:15 output data]]
|-
|-
| 0x14
| 0x14
| 15:0
| 15:0
| DIO 42:27 output data
| [[#DIO|DIO 42:27 output data]]
|-
|-
| rowspan="5" | 0x16
| rowspan="5" | 0x16
| 15
| 15
| Enable UART2 TXEN (override DIO 10)
| [[#XUARTs|Enable UART2 TXEN]] ([[#DIO|override DIO 10]])
|-
|-
| 14
| 14
| Enable UART1 TXEN (override DIO 8)
| [[#XUARTs|Enable UART1 TXEN]] ([[#DIO|override DIO 8]])
|-
|-
| 13
| 13
| Enable UART5 TXEN (override DIO 7)
| [[#XUARTs|Enable UART5 TXEN]] ([[#DIO|override DIO 7]])
|-
|-
| 12
| 12
| Enable UART3 TXEN (override DIO 13)
| [[#XUARTs|Enable UART3 TXEN]] ([[#DIO|override DIO 13]])
|-
|-
| 11:0
| 11:0
| DIO 59:48 output data
| [[#DIO|DIO 59:48 output data]]
|-
|-
| rowspan="2" | 0x18
| rowspan="2" | 0x18
Line 120: Line 120:
|-
|-
| 14:0
| 14:0
| DIO 14:0 data direction
| [[#DIO|DIO DIO 14:0 data direction]]
|-
|-
| rowspan="3" | 0x1a
| rowspan="3" | 0x1a
Line 127: Line 127:
|-
|-
| 10:5
| 10:5
| DIO 26:22 data direction
| [[#DIO|DIO DIO 26:22 data direction]]
|-
|-
| 4:0
| 4:0
| DIO 20:15 data direction
| [[#DIO|DIO DIO 20:15 data direction]]
|-
|-
| 0x1c
| 0x1c
| 15:0
| 15:0
| DIO 42:27 data direction
| [[#DIO|DIO DIO 42:27 data direction]]
|-
|-
| rowspan="2" | 0x1e
| rowspan="2" | 0x1e
Line 141: Line 141:
|-
|-
| 11:0
| 11:0
| DIO 59:48 data direction
| [[#DIO|DIO DIO 59:48 data direction]]
|-  
|-  
| rowspan="2" | 0x20
| rowspan="2" | 0x20
Line 148: Line 148:
|-
|-
| 14:0  
| 14:0  
| DIO 14:0 input data
| [[#DIO|DIO DIO 14:0 input data]]
|-
|-
| rowspan="3" | 0x22
| rowspan="3" | 0x22
Line 155: Line 155:
|-
|-
| 10:5
| 10:5
| DIO 26:22 input data  
| [[#DIO|DIO DIO 26:22 input data]]
|-
|-
| 4:0
| 4:0
| DIO 20:15 input data
| [[#DIO|DIO DIO 20:15 input data]]
|-
|-
| 0x24
| 0x24
| 15:0
| 15:0
| DIO 42:27 input data
| [[#DIO|DIO DIO 42:27 input data]]
|-
|-
| rowspan="2" | 0x26
| rowspan="2" | 0x26
Line 169: Line 169:
|-
|-
| 11:0
| 11:0
| DIO 59:48 input data  
| [[#DIO|DIO DIO 59:48 input data]]
|-
|-
| rowspan="2" | 0x28
| rowspan="2" | 0x28
Line 176: Line 176:
|-
|-
| 3:0
| 3:0
| TAG memory access  
| FPGA TAG memory access
|-
|-
| 0x2a
| 0x2a
| 15:0
| 15:0
| Custom load ID register (reads 0 on standard load)
| Custom load ID register <ref> Reads back 0 on default load.  Used to identify customized bitstreams </ref>
|-
|-
| rowspan="7" | 0x2c  
| rowspan="7" | 0x2c  
Line 187: Line 187:
|-
|-
| 5
| 5
| Offboard IRQ 7
| [[#Interrupts|Offboard IRQ 7]]
|-
|-
| 4
| 4
| Offboard IRQ 6
| [[#Interrupts|Offboard IRQ 6]]
|-
|-
| 3
| 3
| Offboard IRQ 5
| [[#Interrupts|Offboard IRQ 5]]
|-
|-
| 2
| 2
| CAN2 IRQ
| [[#Interrupts|CAN2 IRQ]]
|-
|-
| 1
| 1
| CAN IRQ
| [[#Interrupts|CAN IRQ]]
|-
|-
| 0
| 0
| XUART IRQ
| [[#Interrupts|XUART IRQ]]
|-
|-
| 0x2e
| rowspan="7" | 0x2e  
| 15:0
| 15:6
| IRQ mask register: 1 disables the corresponding IRQ.
| Reserved
|-
| 5
| Offboard IRQ 7 mask (1 disabled, 0 on) <ref name=irqmask>The IRQ masks are handled automatically by the kernel after an IRQ is requested.  Under most circumstances these registers should not be manipulated.</ref>
|-
| 4
| Offboard IRQ 6 mask (1 disabled, 0 on) <ref name=irqmask />
|-
| 3
| Offboard IRQ 5 mask (1 disabled, 0 on)<ref name=irqmask />
|-
| 2
| CAN2 IRQ mask (1 disabled, 0 on)<ref name=irqmask />
|-
| 1
| CAN IRQ mask (1 disabled, 0 on)<ref name=irqmask />
|-
| 0
| XUART IRQ mask (1 disabled, 0 on)<ref name=irqmask />
|-
|-
| 0x30
| 0x30
| 15:0
| 15:0
| DIO 6 Edge Counter 0 (write to clear)
| [[#DIO|DIO 6 Edge Counter 0 (write to clear)]]
|-
|-
| 0x32
| 0x32
| 15:0
| 15:0
| DIO 4 Edge Counter 1 (write to clear)
| [[#DIO|DIO 4 Edge Counter 1 (write to clear)]]
|}
|}

Revision as of 10:11, 10 January 2013

The registers listed below are all 16 bit registers and must be accessed with 16 bit reads and writes. This register block appears at base address 0x80004000.

Offset Bits Usage
0x00 15:0 Model ID: Reads 0x4700
0x02 15 Reset switch enable (Use DIO 9 input)
14 Enable touchscreen (override DIO 30-35)
13 Enable UART4 TXEN (override DIO 14)
12 Enable UART0 TXEN (override DIO 12)
11 Enable 12.5MHz base board clock (override DIO 3)
10 Enable SPI (override DIO 17-20)
9 Enable 2nd CAN (override DIO 10,11)
8 Enable CAN (override DIO 15,16)
7:6 Scratch Register
5 Mode2
4 Mode1
3:0 FPGA revision
0x04 15:0 Muxbus configuration register
0x06 15:0 Watchdog feed register
0x08 15:0 Free running 1MHz counter LSB
0x0a 15:0 Free running 1MHz counter MSB
0x0c 15:0 Hardware RNG LSB
0x0e 15:0 Hardware RNG MSB
0x10 15 Reserved
14:0 DIO 14:0 output data
0x12 15:13 Reserved
12 Red LED (1 = on)
11 Green LED (1 = on)
10:5 DIO 26:22 output data
4:0 DIO 20:15 output data
0x14 15:0 DIO 42:27 output data
0x16 15 Enable UART2 TXEN (override DIO 10)
14 Enable UART1 TXEN (override DIO 8)
13 Enable UART5 TXEN (override DIO 7)
12 Enable UART3 TXEN (override DIO 13)
11:0 DIO 59:48 output data
0x18 15 Reserved
14:0 DIO DIO 14:0 data direction
0x1a 15:11 Reserved
10:5 DIO DIO 26:22 data direction
4:0 DIO DIO 20:15 data direction
0x1c 15:0 DIO DIO 42:27 data direction
0x1e 15:12 Reserved
11:0 DIO DIO 59:48 data direction
0x20 15 Reserved
14:0 DIO DIO 14:0 input data
0x22 15:11 Reserved
10:5 DIO DIO 26:22 input data
4:0 DIO DIO 20:15 input data
0x24 15:0 DIO DIO 42:27 input data
0x26 15:12 Reserved
11:0 DIO DIO 59:48 input data
0x28 15:4 Reserved
3:0 FPGA TAG memory access
0x2a 15:0 Custom load ID register [1]
0x2c 15:6 Reserved
5 Offboard IRQ 7
4 Offboard IRQ 6
3 Offboard IRQ 5
2 CAN2 IRQ
1 CAN IRQ
0 XUART IRQ
0x2e 15:6 Reserved
5 Offboard IRQ 7 mask (1 disabled, 0 on) [2]
4 Offboard IRQ 6 mask (1 disabled, 0 on) [2]
3 Offboard IRQ 5 mask (1 disabled, 0 on)[2]
2 CAN2 IRQ mask (1 disabled, 0 on)[2]
1 CAN IRQ mask (1 disabled, 0 on)[2]
0 XUART IRQ mask (1 disabled, 0 on)[2]
0x30 15:0 DIO 6 Edge Counter 0 (write to clear)
0x32 15:0 DIO 4 Edge Counter 1 (write to clear)
  1. ↑ Reads back 0 on default load. Used to identify customized bitstreams
  2. ↑ 2.0 2.1 2.2 2.3 2.4 2.5 The IRQ masks are handled automatically by the kernel after an IRQ is requested. Under most circumstances these registers should not be manipulated.
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