4700 Syscon: Difference between revisions
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| [[#DIO|DIO 4 Edge Counter 1 (write to clear)]] | | [[#DIO|DIO 4 Edge Counter 1 (write to clear)]] | ||
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Revision as of 10:11, 10 January 2013
The registers listed below are all 16 bit registers and must be accessed with 16 bit reads and writes. This register block appears at base address 0x80004000.
Offset | Bits | Usage |
---|---|---|
0x00 | 15:0 | Model ID: Reads 0x4700 |
0x02 | 15 | Reset switch enable (Use DIO 9 input) |
14 | Enable touchscreen (override DIO 30-35) | |
13 | Enable UART4 TXEN (override DIO 14) | |
12 | Enable UART0 TXEN (override DIO 12) | |
11 | Enable 12.5MHz base board clock (override DIO 3) | |
10 | Enable SPI (override DIO 17-20) | |
9 | Enable 2nd CAN (override DIO 10,11) | |
8 | Enable CAN (override DIO 15,16) | |
7:6 | Scratch Register | |
5 | Mode2 | |
4 | Mode1 | |
3:0 | FPGA revision | |
0x04 | 15:0 | Muxbus configuration register |
0x06 | 15:0 | Watchdog feed register |
0x08 | 15:0 | Free running 1MHz counter LSB |
0x0a | 15:0 | Free running 1MHz counter MSB |
0x0c | 15:0 | Hardware RNG LSB |
0x0e | 15:0 | Hardware RNG MSB |
0x10 | 15 | Reserved |
14:0 | DIO 14:0 output data | |
0x12 | 15:13 | Reserved |
12 | Red LED (1 = on) | |
11 | Green LED (1 = on) | |
10:5 | DIO 26:22 output data | |
4:0 | DIO 20:15 output data | |
0x14 | 15:0 | DIO 42:27 output data |
0x16 | 15 | Enable UART2 TXEN (override DIO 10) |
14 | Enable UART1 TXEN (override DIO 8) | |
13 | Enable UART5 TXEN (override DIO 7) | |
12 | Enable UART3 TXEN (override DIO 13) | |
11:0 | DIO 59:48 output data | |
0x18 | 15 | Reserved |
14:0 | DIO DIO 14:0 data direction | |
0x1a | 15:11 | Reserved |
10:5 | DIO DIO 26:22 data direction | |
4:0 | DIO DIO 20:15 data direction | |
0x1c | 15:0 | DIO DIO 42:27 data direction |
0x1e | 15:12 | Reserved |
11:0 | DIO DIO 59:48 data direction | |
0x20 | 15 | Reserved |
14:0 | DIO DIO 14:0 input data | |
0x22 | 15:11 | Reserved |
10:5 | DIO DIO 26:22 input data | |
4:0 | DIO DIO 20:15 input data | |
0x24 | 15:0 | DIO DIO 42:27 input data |
0x26 | 15:12 | Reserved |
11:0 | DIO DIO 59:48 input data | |
0x28 | 15:4 | Reserved |
3:0 | FPGA TAG memory access | |
0x2a | 15:0 | Custom load ID register [1] |
0x2c | 15:6 | Reserved |
5 | Offboard IRQ 7 | |
4 | Offboard IRQ 6 | |
3 | Offboard IRQ 5 | |
2 | CAN2 IRQ | |
1 | CAN IRQ | |
0 | XUART IRQ | |
0x2e | 15:6 | Reserved |
5 | Offboard IRQ 7 mask (1 disabled, 0 on) [2] | |
4 | Offboard IRQ 6 mask (1 disabled, 0 on) [2] | |
3 | Offboard IRQ 5 mask (1 disabled, 0 on)[2] | |
2 | CAN2 IRQ mask (1 disabled, 0 on)[2] | |
1 | CAN IRQ mask (1 disabled, 0 on)[2] | |
0 | XUART IRQ mask (1 disabled, 0 on)[2] | |
0x30 | 15:0 | DIO 6 Edge Counter 0 (write to clear) |
0x32 | 15:0 | DIO 4 Edge Counter 1 (write to clear) |