4700 Syscon: Difference between revisions

From embeddedTS Manuals
(fixed 0x22 off-by-one documentation error.)
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The registers listed below are all 16 bit registers and must be accessed with 16 bit reads and writes. This register block appears at base address 0x80004000.  For example, to identify the TS-4700:
<source lang=bash>
peekpoke 16 0x80004000
</source>
This will return 0x4700 to read back the model ID. 
Many of the syscon options can be manipulated using ts4700ctl.
  Usage: ts4700ctl [OPTION] ...
  Technologic Systems TS-4700 FPGA manipulation.
 
  General options:
    -g, --getmac            Display ethernet MAC address
    -s, --setmac=MAC        Set ethernet MAC address
    -R, --reboot            Reboot the board
    -i, --info              Display board FPGA info
    -B, --baseboard        Display baseboard ID
    -a, --adc              Display MCP3428 ADC readings in millivolts
    -e, --greenledon        Turn green LED on
    -b, --greenledoff      Turn green LED off
    -c, --redledon          Turn red LED on
    -d, --redledoff        Turn red LED off
    -D, --setdio=LVAL      Set DIO output to LVAL
    -O, --setdiodir=LVAL    Set DIO direction to LVAL (1 - output)
    -G, --getdio            Get DIO input
    -Z, --getdioreg        Get DIO direction and output register values
    -x, --random            Get 16-bit hardware random number
    -W, --watchdog          Daemonize and set up /dev/watchdog
    -A, --autofeed=SETTING  Daemonize and auto feed watchdog
    -n, --setrng            Seed the kernel random number generator
    -X, --resetswitchon    Enable reset switch
    -Y, --resetswitchoff    Disable reset switch
    -l, --loadfpga=FILE    Load FPGA bitstream from FILE
    -k  --clocks            Display the CPU/DRAM clock speeds from FPGA tagmem
    -q  --cputemp          Display the CPU die temperature
    -h, --help              This help


The registers listed below are all 16 bit registers and must be accessed with 16 bit reads and writes. This register block appears at base address 0x80004000.


{| class=wikitable
{| class=wikitable
Line 13: Line 48:
| rowspan="12" | 0x02
| rowspan="12" | 0x02
| 15
| 15
| Reset switch enable (Use DIO 9 input)
| [[#DIO|Reset switch enable (Use DIO 9 input)]]
|-
|-
| 14
| 14
| Enable touchscreen (override DIO 30-35)
| [[#Touchscreen Controller|Enable touchscreen]] [[#DIO|(override DIO 30-35)]]
|-
|-
| 13
| 13
| Enable UART4 TXEN (override DIO 14)
| [[#XUARTs|Enable UART4 TXEN]] [[#DIO|(override DIO 14)]]
|-
|-
| 12
| 12
| Enable UART0 TXEN (override DIO 12)
| [[#XUARTs|Enable UART0 TXEN]] [[#DIO|(override DIO 12)]]
|-
|-
| 11
| 11
| Enable 12.5MHz base board clock (override DIO 3)
| [[#DIO|Enable 12.5MHz base board clock (override DIO 3)]]
|-
|-
| 10
| 10
| Enable SPI (override DIO 17-20)  
| [[#SPI|Enable SPI]] ([[#DIO|override DIO 17-20]])
|-
|-
| 9
| 9
| Enable 2nd CAN (override DIO 10,11)
| [[#CAN|Enable 2nd CAN]] ([[#DIO|override DIO 10,11]])
|-
|-
| 8
| 8
| Enable CAN (override DIO 15,16)  
| [[#CAN|Enable CAN]] ([[#DIO|override DIO 15,16]])  
|-
|-
| 7:6
| 7:6
| Scratch Register (used by bootrom)
| Scratch Register
|-
|-
| 5
| 5
| Mode2
| [[#Booting_up_the_board|Mode2]]
|-
|-
| 4
| 4
| Mode1  
| [[#Booting_up_the_board|Mode1]]
|-
|-
| 3:0
| 3:0
Line 50: Line 85:
| 0x04
| 0x04
| 15:0
| 15:0
| Muxbus configuration register
| [[#MUXBUS|Muxbus configuration register]]
|-
|-
| 0x06
| 0x06
| 15:0
| 15:0
| Watchdog feed register
| [[#Watchdog|Watchdog feed register]]
|-
|-
| 0x08
| 0x08
Line 77: Line 112:
|-
|-
| 14:0
| 14:0
| DIO 14:0 output data
| [[#DIO|DIO 14:0 output data]]
|-
|-
| rowspan="5" | 0x12
| rowspan="5" | 0x12
Line 84: Line 119:
|-
|-
| 12
| 12
| Red LED (1 = on)  
| [[#LEDs|Red LED (1 = on)]]
|-
|-
| 11
| 11
| Green LED (1 = on)
| [[#LEDs|Green LED (1 = on)]]
|-
|-
| 10:5
| 10:6
| DIO 26:22 output data
| [[#DIO|DIO 26:22 output data]]
|-
|-
| 4:0
| 5:0
| DIO 20:15 output data
| [[#DIO| DIO 20:15 output data]]
|-
|-
| 0x14
| 0x14
| 15:0
| 15:0
| DIO 42:27 output data
| [[#DIO|DIO 42:27 output data]]
|-
|-
| rowspan="5" | 0x16
| rowspan="5" | 0x16
| 15
| 15
| Enable UART2 TXEN (override DIO 10)
| [[#XUARTs|Enable UART2 TXEN]] ([[#DIO|override DIO 10]])
|-
|-
| 14
| 14
| Enable UART1 TXEN (override DIO 8)
| [[#XUARTs|Enable UART1 TXEN]] ([[#DIO|override DIO 8]])
|-
|-
| 13
| 13
| Enable UART5 TXEN (override DIO 7)
| [[#XUARTs|Enable UART5 TXEN]] ([[#DIO|override DIO 7]])
|-
|-
| 12
| 12
| Enable UART3 TXEN (override DIO 13)
| [[#XUARTs|Enable UART3 TXEN]] ([[#DIO|override DIO 13]])
|-
|-
| 11:0
| 11:0
| DIO 59:48 output data
| [[#DIO|DIO 59:48 output data]]
|-
|-
| rowspan="2" | 0x18
| rowspan="2" | 0x18
Line 120: Line 155:
|-
|-
| 14:0
| 14:0
| DIO 14:0 data direction
| [[#DIO|DIO DIO 14:0 data direction]]
|-
|-
| rowspan="3" | 0x1a
| rowspan="3" | 0x1a
Line 126: Line 161:
| Reserved
| Reserved
|-
|-
| 10:5
| 10:6
| DIO 26:22 data direction
| [[#DIO|DIO DIO 26:22 data direction]]
|-
|-
| 4:0
| 5:0
| DIO 20:15 data direction
| [[#DIO|DIO DIO 20:15 data direction]]
|-
|-
| 0x1c
| 0x1c
| 15:0
| 15:0
| DIO 42:27 data direction
| [[#DIO|DIO DIO 42:27 data direction]]
|-
|-
| rowspan="2" | 0x1e
| rowspan="2" | 0x1e
Line 141: Line 176:
|-
|-
| 11:0
| 11:0
| DIO 59:48 data direction
| [[#DIO|DIO DIO 59:48 data direction]]
|-  
|-  
| rowspan="2" | 0x20
| rowspan="2" | 0x20
Line 148: Line 183:
|-
|-
| 14:0  
| 14:0  
| DIO 14:0 input data
| [[#DIO|DIO DIO 14:0 input data]]
|-
|-
| rowspan="3" | 0x22
| rowspan="3" | 0x22
Line 155: Line 190:
|-
|-
| 10:6
| 10:6
| DIO 26:22 input data  
| [[#DIO|DIO DIO 26:22 input data]]
|-
|-
| 5:0
| 5:0
| DIO 20:15 input data
| [[#DIO|DIO DIO 20:15 input data]]
|-
|-
| 0x24
| 0x24
| 15:0
| 15:0
| DIO 42:27 input data
| [[#DIO|DIO DIO 42:27 input data]]
|-
|-
| rowspan="2" | 0x26
| rowspan="2" | 0x26
Line 169: Line 204:
|-
|-
| 11:0
| 11:0
| DIO 59:48 input data  
| [[#DIO|DIO DIO 59:48 input data]]
|-
|-
| rowspan="2" | 0x28
| rowspan="2" | 0x28
Line 176: Line 211:
|-
|-
| 3:0
| 3:0
| TAG memory access  
| FPGA TAG memory access <ref>TAG memory stores persistent data on the FPGA such a the MAC address, CPU settings, and the born on date.  Software using this data should instead use ts4700ctl rather than accessing this register manually.</ref>
|-
|-
| 0x2a
| 0x2a
| 15:0
| 15:0
| Custom load ID register (reads 0 on standard load)
| Custom load ID register <ref>Reads back 0 on default load.  Used to identify customized bitstreams</ref>
|-
|-
| rowspan="7" | 0x2c  
| rowspan="7" | 0x2c  
Line 187: Line 222:
|-
|-
| 5
| 5
| Offboard IRQ 7
| [[#Interrupts|Offboard IRQ 7]]
|-
| 4
| [[#Interrupts|Offboard IRQ 6]]
|-
| 3
| [[#Interrupts|Offboard IRQ 5]]
|-
| 2
| [[#Interrupts|CAN2 IRQ]]
|-
| 1
| [[#Interrupts|CAN IRQ]]
|-
| 0
| [[#Interrupts|XUART IRQ]]
|-
| rowspan="7" | 0x2e
| 15:6
| Reserved
|-
| 5
| Offboard IRQ 7 mask (1 disabled, 0 on) <ref name=irqmask>The IRQ masks are handled automatically by the kernel after an IRQ is requested.  Under most circumstances these registers should not be manipulated.</ref>
|-
|-
| 4
| 4
| Offboard IRQ 6
| Offboard IRQ 6 mask (1 disabled, 0 on) <ref name=irqmask />
|-
|-
| 3
| 3
| Offboard IRQ 5
| Offboard IRQ 5 mask (1 disabled, 0 on)<ref name=irqmask />
|-
|-
| 2
| 2
| CAN2 IRQ
| CAN2 IRQ mask (1 disabled, 0 on)<ref name=irqmask />
|-
|-
| 1
| 1
| CAN IRQ
| CAN IRQ mask (1 disabled, 0 on)<ref name=irqmask />
|-
|-
| 0
| 0
| XUART IRQ
| XUART IRQ mask (1 disabled, 0 on)<ref name=irqmask />
|-
|-
| 0x2e
| rowspan=3 | 0x34
| 15:0
| 0
| IRQ mask register: 1 disables the corresponding IRQ.
| Enable 14.3MHz baseboard clock on DIO 3
|-
|-
| 0x30
| 1
| 15:0
| USB 5V disable <ref>This toggles a DIO on CN1_04 and requires offboard circuitry on the baseboard to toggle USB power.</ref>
| DIO 6 Edge Counter 0 (write to clear)
|-
|-
| 0x32
| 2
| 15:0
| LCD 3.3V disable <ref>This toggles a DIO on CN1_48 and requires offboard circuitry on the baseboard to toggle LCD power.</ref>
| DIO 4 Edge Counter 1 (write to clear)
|}
|}
<references />

Latest revision as of 18:21, 16 May 2014

The registers listed below are all 16 bit registers and must be accessed with 16 bit reads and writes. This register block appears at base address 0x80004000. For example, to identify the TS-4700: 

peekpoke 16 0x80004000

This will return 0x4700 to read back the model ID.

Many of the syscon options can be manipulated using ts4700ctl. 

 Usage: ts4700ctl [OPTION] ...
 Technologic Systems TS-4700 FPGA manipulation.
 
 General options:
   -g, --getmac            Display ethernet MAC address
   -s, --setmac=MAC        Set ethernet MAC address
   -R, --reboot            Reboot the board
   -i, --info              Display board FPGA info
   -B, --baseboard         Display baseboard ID
   -a, --adc               Display MCP3428 ADC readings in millivolts
   -e, --greenledon        Turn green LED on
   -b, --greenledoff       Turn green LED off
   -c, --redledon          Turn red LED on
   -d, --redledoff         Turn red LED off
   -D, --setdio=LVAL       Set DIO output to LVAL
   -O, --setdiodir=LVAL    Set DIO direction to LVAL (1 - output)
   -G, --getdio            Get DIO input
   -Z, --getdioreg         Get DIO direction and output register values
   -x, --random            Get 16-bit hardware random number
   -W, --watchdog          Daemonize and set up /dev/watchdog
   -A, --autofeed=SETTING  Daemonize and auto feed watchdog
   -n, --setrng            Seed the kernel random number generator
   -X, --resetswitchon     Enable reset switch
   -Y, --resetswitchoff    Disable reset switch
   -l, --loadfpga=FILE     Load FPGA bitstream from FILE
   -k  --clocks            Display the CPU/DRAM clock speeds from FPGA tagmem
   -q  --cputemp           Display the CPU die temperature
   -h, --help              This help


Offset Bits Usage
0x00 15:0 Model ID: Reads 0x4700
0x02 15 Reset switch enable (Use DIO 9 input)
14 Enable touchscreen (override DIO 30-35)
13 Enable UART4 TXEN (override DIO 14)
12 Enable UART0 TXEN (override DIO 12)
11 Enable 12.5MHz base board clock (override DIO 3)
10 Enable SPI (override DIO 17-20)
9 Enable 2nd CAN (override DIO 10,11)
8 Enable CAN (override DIO 15,16)
7:6 Scratch Register
5 Mode2
4 Mode1
3:0 FPGA revision
0x04 15:0 Muxbus configuration register
0x06 15:0 Watchdog feed register
0x08 15:0 Free running 1MHz counter LSB
0x0a 15:0 Free running 1MHz counter MSB
0x0c 15:0 Hardware RNG LSB
0x0e 15:0 Hardware RNG MSB
0x10 15 Reserved
14:0 DIO 14:0 output data
0x12 15:13 Reserved
12 Red LED (1 = on)
11 Green LED (1 = on)
10:6 DIO 26:22 output data
5:0 DIO 20:15 output data
0x14 15:0 DIO 42:27 output data
0x16 15 Enable UART2 TXEN (override DIO 10)
14 Enable UART1 TXEN (override DIO 8)
13 Enable UART5 TXEN (override DIO 7)
12 Enable UART3 TXEN (override DIO 13)
11:0 DIO 59:48 output data
0x18 15 Reserved
14:0 DIO DIO 14:0 data direction
0x1a 15:11 Reserved
10:6 DIO DIO 26:22 data direction
5:0 DIO DIO 20:15 data direction
0x1c 15:0 DIO DIO 42:27 data direction
0x1e 15:12 Reserved
11:0 DIO DIO 59:48 data direction
0x20 15 Reserved
14:0 DIO DIO 14:0 input data
0x22 15:11 Reserved
10:6 DIO DIO 26:22 input data
5:0 DIO DIO 20:15 input data
0x24 15:0 DIO DIO 42:27 input data
0x26 15:12 Reserved
11:0 DIO DIO 59:48 input data
0x28 15:4 Reserved
3:0 FPGA TAG memory access [1]
0x2a 15:0 Custom load ID register [2]
0x2c 15:6 Reserved
5 Offboard IRQ 7
4 Offboard IRQ 6
3 Offboard IRQ 5
2 CAN2 IRQ
1 CAN IRQ
0 XUART IRQ
0x2e 15:6 Reserved
5 Offboard IRQ 7 mask (1 disabled, 0 on) [3]
4 Offboard IRQ 6 mask (1 disabled, 0 on) [3]
3 Offboard IRQ 5 mask (1 disabled, 0 on)[3]
2 CAN2 IRQ mask (1 disabled, 0 on)[3]
1 CAN IRQ mask (1 disabled, 0 on)[3]
0 XUART IRQ mask (1 disabled, 0 on)[3]
0x34 0 Enable 14.3MHz baseboard clock on DIO 3
1 USB 5V disable [4]
2 LCD 3.3V disable [5]
  1. ↑ TAG memory stores persistent data on the FPGA such a the MAC address, CPU settings, and the born on date. Software using this data should instead use ts4700ctl rather than accessing this register manually.
  2. ↑ Reads back 0 on default load. Used to identify customized bitstreams
  3. ↑ 3.0 3.1 3.2 3.3 3.4 3.5 The IRQ masks are handled automatically by the kernel after an IRQ is requested. Under most circumstances these registers should not be manipulated.
  4. ↑ This toggles a DIO on CN1_04 and requires offboard circuitry on the baseboard to toggle USB power.
  5. ↑ This toggles a DIO on CN1_48 and requires offboard circuitry on the baseboard to toggle LCD power.
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