4700 Syscon
From embeddedTS Manuals
The registers listed below are all 16 bit registers and must be accessed with 16 bit reads and writes. This register block appears at base address 0x80004000.
Offset | Bits | Usage |
---|---|---|
0x00 | 15:0 | Model ID: Reads 0x4700 |
0x02 | 15 | Reset switch enable (Use DIO 9 input) |
14 | Enable touchscreen (override DIO 30-35) | |
13 | Enable UART4 TXEN (override DIO 14) | |
12 | Enable UART0 TXEN (override DIO 12) | |
11 | Enable 12.5MHz base board clock (override DIO 3) | |
10 | Enable SPI (override DIO 17-20) | |
9 | Enable 2nd CAN (override DIO 10,11) | |
8 | Enable CAN (override DIO 15,16) | |
7:6 | Scratch Register (used by bootrom) | |
5:4 | Mode2, Mode1 | |
3:0 | FPGA revision | |
0x04 | 15:0 | External bus config register |
0x06 | 15:0 | Watchdog feed register |
0x08 | 15:0 | Free running 1MHz counter LSB |
0x0a | 15:0 | Free running 1MHz counter MSB |
0x0c | 15:0 | Hardware RNG LSB |
0x0e | 15:0 | Hardware RNG MSB |
0x10 | 15 | Reserved |
14:0 | DIO group 1 output data | |
0x12 | 15:13 | Reserved |
12 | Red LED (1 = on) | |
11 | Green LED (1 = on) | |
10:0 | DIO group 2 output data | |
0x14 | 15:0 | DIO group 3 output data |
0x16 | 15 | Enable UART2 TXEN (override DIO 10) |
14 | Enable UART1 TXEN (override DIO 8) | |
13 | Enable UART5 TXEN (override DIO 7) | |
12 | Enable UART3 TXEN (override DIO 13) | |
11:0 | DIO group 4 output data | |
0x18 | 15 | Reserved |
14:0 | DIO group 1 data direction | |
0x1a | 15:11 | Reserved |
10:0 | DIO group 2 data direction | |
0x1c | 15:0 | DIO group 3 data direction |
0x1e | 15:12 | Reserved |
11:0 | DIO group 4 data direction | |
0x20 | 15 | Reserved |
14:0 | DIO group 1 input data | |
0x22 | 15:11 | Reserved |
10:0 | DIO group 2 input data | |
0x24 | 15:0 | DIO group 3 input data |
0x26 | 15:12 | Reserved |
11:0 | DIO group 4 input data | |
0x28 | 15:4 | Reserved |
3:0 | TAG memory access | |
0x2a | 15:0 | Custom load ID register (reads 0 on standard load) |
0x2c | 15:6 | Reserved for future IRQs |
5 | Offboard IRQ 7 | |
4 | Offboard IRQ 6 | |
3 | Offboard IRQ 5 | |
2 | CAN2 IRQ | |
1 | CAN IRQ | |
0 | XUART IRQ | |
0x2e | 15:0 | IRQ mask register: 1 disables the corresponding IRQ. |
0x30 | 15:0 | Edge Counter 0 |
0x32 | 15:0 | Edge Counter 1 |