4710 FPGA bitstreams: Difference between revisions

From embeddedTS Manuals
(Created page with "The FPGA has the capability to be reloaded on startup and reprogram itself with different configurations. The default bitstream is hardcoded into the FPGA, but the soft reloa...")
 
m (Links auto-updated for 2022 re-branding ( https://files.embeddedarm.com/ts-socket-macrocontrollers/ts-4710-linux/binaries/ts-bitstreams/ts4710-fpga-rev4-default-ADC.vme.bz2 →‎ https://files.embeddedTS.com/ts-socket-macrocontrollers/ts-4710-linux/binaries/ts-bitstreams/ts4710-fpga-rev4-default-ADC.vme.bz2 http://www.embeddedarm.com/support/contact-us.php →‎ http://www.embeddedTS.com/support/contact-us.php))
 
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The FPGA has the capability to be reloaded on startup and reprogram itself with different configurations.  The default bitstream is hardcoded into the FPGA, but the soft reloaded bitstreams can be placed in /ts4700_bitstream.vme.gz on the initrd root to make the board load the bitstream on startup.  If we do not have a configuration you need, you can [[#FPGA Programming|build a new bitstream]], or [http://www.embeddedarm.com/support/contact-us.php contact us] for our engineering services.
The FPGA has the capability to be reloaded on startup and reprogram itself with different configurations.  The default bitstream is hardcoded into the FPGA, but the soft reloaded bitstreams can be placed in /ts/ts<model>-fpga.vme.gz on the Debian root to make the board load the bitstream on startup.  If we do not have a configuration you need, you can [[#FPGA Programming|build a new bitstream]], or [http://www.embeddedTS.com/support/contact-us.php contact us] for our engineering services.


{| class=wikitable
{| class=wikitable
Line 5: Line 5:
! XUARTs
! XUARTs
! CAN
! CAN
! CAN2
! Touchscreen
! Touchscreen
! SPI
! SPI
! ADC
|-
|-
| Default (8K LUT)
| Default (8K LUT)
| 0-6
| On
| On
| On
| Off
|-
| [https://files.embeddedTS.com/ts-socket-macrocontrollers/ts-4710-linux/binaries/ts-bitstreams/ts4710-fpga-rev4-default-ADC.vme.bz2 ts4710-fpga-rev4-default-ADC.vme.bz2]
| 0-6
| 0-6
| On
| On

Latest revision as of 16:24, 17 January 2022

The FPGA has the capability to be reloaded on startup and reprogram itself with different configurations. The default bitstream is hardcoded into the FPGA, but the soft reloaded bitstreams can be placed in /ts/ts<model>-fpga.vme.gz on the Debian root to make the board load the bitstream on startup. If we do not have a configuration you need, you can build a new bitstream, or contact us for our engineering services.

Bitstream XUARTs CAN Touchscreen SPI ADC
Default (8K LUT) 0-6 On On On Off
ts4710-fpga-rev4-default-ADC.vme.bz2 0-6 On On On On