4710 FPGA bitstreams

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Revision as of 17:19, 26 February 2013 by Mark (talk | contribs) (Created page with "The FPGA has the capability to be reloaded on startup and reprogram itself with different configurations. The default bitstream is hardcoded into the FPGA, but the soft reloa...")
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The FPGA has the capability to be reloaded on startup and reprogram itself with different configurations. The default bitstream is hardcoded into the FPGA, but the soft reloaded bitstreams can be placed in /ts4700_bitstream.vme.gz on the initrd root to make the board load the bitstream on startup. If we do not have a configuration you need, you can build a new bitstream, or contact us for our engineering services.

Bitstream XUARTs CAN CAN2 Touchscreen SPI
Default (8K LUT) 0-6 On On On On
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