TS-4100 CPU DIO Table: Difference between revisions

From embeddedTS Manuals
(Partial convert to chip/bank notation for new character GPIO interface)
(Finalized revised CPU GPIO table)
Line 6: Line 6:
! Pin
! Pin
! Name
! Name
! REMOVE
 
! Functions <ref>Common functions for the pin. Default kernel function is denoted with parenthesis "()"</ref>
! Functions <ref>Common functions for the pin. Default kernel function is denoted with parenthesis "()"</ref>
! Location
! Location
Line 13: Line 13:
| 0
| 0
| USB_OTG1_ID
| USB_OTG1_ID
|
| ([[#USB|USB1 OTG ID]]) / GPIO
| ([[#USB|USB1 OTG ID]]) / GPIO
| [[#TS-SOCKET|CN2_074]]
| [[#TS-SOCKET|CN2_074]]
Line 20: Line 19:
| 1
| 1
| GPIO_1_ADC
| GPIO_1_ADC
|
| (GPIO) / [[#ADC|ADC input]]
| (GPIO) / [[#ADC|ADC input]]
| [[#TS-SOCKET|CN2_012]]
| [[#TS-SOCKET|CN2_012]]
Line 27: Line 25:
| 8
| 8
| LCD_PWM_ADC8
| LCD_PWM_ADC8
|
| ([[#PWM|PWM]]) / [[#ADC|ADC input]] / GPIO
| ([[#PWM|PWM]]) / [[#ADC|ADC input]] / GPIO
| [[#TS-SOCKET|CN1_057]]
| [[#TS-SOCKET|CN1_057]]
Line 34: Line 31:
| 9
| 9
| GPIO_9_ADC
| GPIO_9_ADC
|
| ([[#PWM|PWM]]) / [[#ADC|ADC input]] / GPIO
| ([[#PWM|PWM]]) / [[#ADC|ADC input]] / GPIO
| [[#TS-SOCKET|CN2_091]]
| [[#TS-SOCKET|CN2_091]]
Line 41: Line 37:
| 10
| 10
| EN_ETH_PHY_PWR
| EN_ETH_PHY_PWR
|
| ([[#Ethernet|Ethernet PHY power en.]]) / GPIO
| ([[#Ethernet|Ethernet PHY power en.]]) / GPIO
| [[#TS-SOCKET|CN2_046]]
| [[#TS-SOCKET|CN2_046]]
Line 48: Line 43:
| 11
| 11
| AUD_MCLK
| AUD_MCLK
|
| ([[#I2S|I2S Master Clock]]) / GPIO
| ([[#I2S|I2S Master Clock]]) / GPIO
| [[#TS-SOCKET|CN2_054]]
| [[#TS-SOCKET|CN2_054]]
Line 55: Line 49:
| 12
| 12
| AUD_FRM
| AUD_FRM
|
| ([[#I2S|I2S TX Sync]]) / GPIO
| ([[#I2S|I2S TX Sync]]) / GPIO
| [[#TS-SOCKET|CN2_038]]
| [[#TS-SOCKET|CN2_038]]
Line 62: Line 55:
| 13
| 13
| AUD_CLK
| AUD_CLK
|
| ([[#I2S|I2S TX Bit Clock]]) / GPIO
| ([[#I2S|I2S TX Bit Clock]]) / GPIO
| [[#TS-SOCKET|CN2_036]]
| [[#TS-SOCKET|CN2_036]]
Line 69: Line 61:
| 14
| 14
| AUD_RXD
| AUD_RXD
|
| ([[#I2S|I2S RX Data]]) / GPIO
| ([[#I2S|I2S RX Data]]) / GPIO
| [[#TS-SOCKET|CN2_042]]
| [[#TS-SOCKET|CN2_042]]
Line 76: Line 67:
| 15
| 15
| AUD_TXD
| AUD_TXD
|
| ([[#I2S|I2S TX Data]]) / GPIO
| ([[#I2S|I2S TX Data]]) / GPIO
| [[#TS-SOCKET|CN2_040]]
| [[#TS-SOCKET|CN2_040]]
Line 83: Line 73:
| 16
| 16
| CONSOLE_TXD
| CONSOLE_TXD
|
| ([[#UARTs|Console UART]]) / GPIO
| ([[#UARTs|Console UART]]) / GPIO
| [[#TS-SOCKET|CN2_093]] / [[#Supervisory Microcontroller|Microcontroller]]
| [[#TS-SOCKET|CN2_093]] / [[#Supervisory Microcontroller|Microcontroller]]
Line 90: Line 79:
| 17
| 17
| CONSOLE_RXD
| CONSOLE_RXD
|
| ([[#UARTs|Console UART]]) / GPIO
| ([[#UARTs|Console UART]]) / GPIO
| [[#TS-SOCKET|CN2_095]] / [[#Supervisory Microcontroller|Microcontroller]]
| [[#TS-SOCKET|CN2_095]] / [[#Supervisory Microcontroller|Microcontroller]]
Line 97: Line 85:
| 18
| 18
| SPARE_1
| SPARE_1
|
| (GPIO)
| (GPIO)
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar]]
Line 104: Line 91:
| 19
| 19
| SPARE_2
| SPARE_2
|
| (GPIO)
| (GPIO)
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar]]
Line 111: Line 97:
| 20
| 20
| UART2_TXD
| UART2_TXD
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#TS-SOCKET|CN2_082]]
| [[#TS-SOCKET|CN2_082]]
Line 118: Line 103:
| 21
| 21
| UART2_RXD
| UART2_RXD
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#TS-SOCKET|CN2_084]]
| [[#TS-SOCKET|CN2_084]]
Line 125: Line 109:
| 22
| 22
| CAN_2_TXD
| CAN_2_TXD
|
| ([[#CAN|CAN TX]]) / GPIO
| ([[#CAN|CAN TX]]) / GPIO
| [[#TS-SOCKET|CN1_071]]
| [[#TS-SOCKET|CN1_071]]
Line 132: Line 115:
| 23
| 23
| CAN_2_RXD
| CAN_2_RXD
|
| ([[#CAN|CAN RX]]) / GPIO
| ([[#CAN|CAN RX]]) / GPIO
| [[#TS-SOCKET|CN1_069]]
| [[#TS-SOCKET|CN1_069]]
Line 139: Line 121:
| 24
| 24
| UART3_TXD
| UART3_TXD
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART3 TX]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
Line 146: Line 127:
| 25
| 25
| UART3_RXD
| UART3_RXD
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART3 RX]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
Line 153: Line 133:
| 26
| 26
| UART3_CTS
| UART3_CTS
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART3 CTS]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
Line 160: Line 139:
| 27
| 27
| UART3_RTS
| UART3_RTS
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART3 RTS]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]  
| [[#Crossbar|FPGA Crossbar]]  
|-
|-
Line 167: Line 145:
| 28
| 28
| UART4_TXD
| UART4_TXD
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART4 TX]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
Line 174: Line 151:
| 29
| 29
| UART4_RXD
| UART4_RXD
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART4 RX]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
Line 181: Line 157:
| 30
| 30
| UART5_TXD
| UART5_TXD
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART5 TX]]) / GPIO
| [[#TS-SOCKET|CN2_090]]
| [[#TS-SOCKET|CN2_090]]
|-
|-
Line 188: Line 163:
| 31
| 31
| UART5_RXD
| UART5_RXD
|
| ([[#UARTs|UART]]) / GPIO
| ([[#UARTs|UART5 RX]]) / GPIO
| [[#TS-SOCKET|CN2_092]]
| [[#TS-SOCKET|CN2_092]]
|-
|-
| CAM_D_0
| 2
| CSI_DATA00
| 0
| 117
| LCD_PIX_CLK
| [[#Camera Interface]] / GPIO
| (GPIO) / [[#LCD Interface|LCD CLK]]
| CN2_052
| [[#TS-SOCKET|CN1_049]]
|-
|-
| CAM_D_1
| 2
| CSI_DATA01
| 1
| 118
| LCD_DE
| [[#Camera Interface]] / GPIO
| (GPIO) / [[#LCD Interface|LCD DE]]
| CN2_056
| [[#TS-SOCKET|CN1_055]]
|-
|-
| CAM_D_2
| 2
| CSI_DATA02
| 2
| 119
| LCD_HSYNC
| [[#Camera Interface]] / GPIO
| (GPIO) / [[#LCD Interface|LCD HSYNC]]
| CN2_058
| [[#TS-SOCKET|CN1_051]]
|-
|-
| CAM_D_3
| 2
| CSI_DATA03
| 3
| 120
| LCD_VSYNC
| [[#Camera Interface]] / GPIO
| (GPIO) / [[#LCD Interface|LCD VSYNC]]
| CN2_060
| [[#TS-SOCKET|CN1_053]]
|-
| CAM_D_4
| CSI_DATA04
| 121
| [[#Camera Interface]] / GPIO
| CN2_062
|-
| CAM_D_5
| CSI_DATA05
| 122
| [[#Camera Interface]] / GPIO
| CN2_064
|-
| CAM_D_6
| CSI_DATA06
| 123
| [[#Camera Interface]] / GPIO
| CN2_066
|-
| CAM_D_7
| CSI_DATA07
| 124
| [[#Camera Interface]] / GPIO
| CN2_068
|-
| CAM_HSYNC
| CSI_HSYNC
| 116
| [[#Camera Interface]] / GPIO
| CN2_070
|-
| CAM_MCLK
| CSI_MCLK
| 113
| [[#Camera Interface]] / GPIO
| CN2_034
|-
| CAM_PIX_CLK
| CSI_PIXCLK
| 114
| [[#Camera Interface]] / GPIO
| CN2_032
|-
| CAM_VSYNC
| CSI_VSYNC
| 115
| [[#Camera Interface]] / GPIO
| CN2_072
|-
| POWER_FAIL
| SNVS_TAMPER0
| 128
| Power Notification <ref>This will assert high when power is disconnected and the system and the board is running off supercaps if populated.</ref>
| Onboard PWR Monitor
|-
| FPGA_IRQ
| SNVS_TAMPER1
| 129
| [[#FPGA]]
| [[#FPGA|FPGA Crossbar]] (Default NC)
|-
| EN_FPGA_PWR
| SNVS_TAMPER2
| 130
| FPGA 3.3V switch
| Onboard FET
|-
| GPIO_DVFS
| SNVS_TAMPER3
| 131
| CPU DVFS <ref>Under almost all cases this should be maintained by the kernel</ref>
| Onboard Regulator
|-
| JTAG_FPGA_TDO
| SNVS_TAMPER4
| 132
| FPGA JTAG
| [[#FPGA|FPGA JTAG pin]]
|-
| JTAG_FPGA_TDI
| SNVS_TAMPER5
| 133
| FPGA JTAG
| [[#FPGA|FPGA JTAG pin]]
|-
| JTAG_FPGA_TMS
| SNVS_TAMPER6
| 134
| FPGA JTAG
| [[#FPGA|FPGA JTAG pin]]
|-
| JTAG_FPGA_TCK
| SNVS_TAMPER7
| 135
| FPGA JTAG
| [[#FPGA|FPGA JTAG pin]]
|-
| SPARE_4
| SNVS_TAMPER8
| 136
| GPIO
| [[#FPGA|FPGA Crossbar]] (Default WIFI IRQ)
|-
| EN_SD_POWER
| SNVS_TAMPER9
| 137
| SD power enable
| Onboard Regulator
|-
| I2C_3_DAT
| LCD_DATA00
| 69
| [[#I2C]] <ref name=fpgaio>This i2c bus is used to access all of the FPGA GPIO and typically should not be repurposed as GPIO.</ref>
| CN2_030, HD1 pin 10
|-
| I2C_3_CLK
| LCD_DATA01
| 70
| [[#I2C]] <ref name=fpgaio />
| CN2_028, HD1 pin 8
|-
|-
| 2
| 7
| LCD_D02
| LCD_D02
| LCD_DATA02
| (GPIO) / [[#LCD Interface|LCD D02]]
| 71
| [[#TS-SOCKET|CN1_028]]
| [[#Parallel LCD Interface]], GPIO
| CN1_028
|-
|-
| 2
| 8
| LCD_D03
| LCD_D03
| LCD_DATA03
| (GPIO) / [[#LCD Interface|LCD D03]]
| 72
| [[#TS-SOCKET|CN1_030]]
| [[#Parallel LCD Interface]], GPIO
| CN1_030
|-
|-
| 2
| 9
| LCD_D04
| LCD_D04
| LCD_DATA04
| (GPIO) / [[#LCD Interface|LCD D04]]
| 73
| [[#TS-SOCKET|CN1_032]]
| [[#Parallel LCD Interface]], GPIO
| CN1_032
|-
|-
| 2
| 10
| LCD_D05
| LCD_D05
| LCD_DATA05
| (GPIO) / [[#LCD Interface|LCD D05]]
| 74
| [[#TS-SOCKET|CN1_034]]
| [[#Parallel LCD Interface]], GPIO
| CN1_034
|-
|-
| 2
| 11
| LCD_D06
| LCD_D06
| LCD_DATA06
| (GPIO) / [[#LCD Interface|LCD D06]]
| 75
| [[#TS-SOCKET|CN1_038]]
| [[#Parallel LCD Interface]], GPIO
| CN1_038
|-
|-
| 2
| 12
| LCD_D07
| LCD_D07
| LCD_DATA07
| (GPIO) / [[#LCD Interface|LCD D07]]
| 76
| [[#TS-SOCKET|CN1_040]]
| [[#Parallel LCD Interface]], GPIO
| CN1_040
|-
|-
| 2
| 13
| CAN_1_TXD
| CAN_1_TXD
| LCD_DATA08
| ([[#CAN|CAN0 TX]]) / GPIO
| 77
| [[#TS-SOCKET|CN2_097]]
| [[#CAN]], GPIO
| CN2_097
|-
|-
| 2
| 14
| CAN_1_RXD
| CAN_1_RXD
| LCD_DATA09
| ([[#CAN|CAN0 RX]]) / GPIO
| 78
| [[#TS-SOCKET|CN2_099]]
| [[#CAN]], GPIO
| CN2_099
|-
|-
| 2
| 15
| LCD_D10
| LCD_D10
| LCD_DATA10
| (GPIO) / [[#LCD Interface|LCD D10]]
| 79
| [[#TS-SOCKET|CN1_023]]
| [[#Parallel LCD Interface]], GPIO
| CN1_023
|-
|-
| 2
| 16
| LCD_D11
| LCD_D11
| LCD_DATA11
| (GPIO) / [[#LCD Interface|LCD D11]]
| 80
| [[#TS-SOCKET|CN1_025]]
| [[#Parallel LCD Interface]], GPIO
| CN1_025
|-
|-
| 2
| 17
| LCD_D12
| LCD_D12
| LCD_DATA12
| (GPIO) / [[#LCD Interface|LCD D12]]
| 81
| [[#TS-SOCKET|CN1_027]]
| [[#Parallel LCD Interface]], GPIO
| CN1_027
|-
|-
| 2
| 18
| LCD_D13
| LCD_D13
| LCD_DATA13
| (GPIO) / [[#LCD Interface|LCD D13]]
| 82
| [[#TS-SOCKET|CN1_031]]
| [[#Parallel LCD Interface]], GPIO
| CN1_031
|-
|-
| 2
| 19
| LCD_D14
| LCD_D14
| LCD_DATA14
| (GPIO) / [[#LCD Interface|LCD D14]]
| 83
| [[#TS-SOCKET|CN1_033]]
| [[#Parallel LCD Interface]], GPIO
| CN1_033
|-
|-
| 2
| 20
| LCD_D15
| LCD_D15
| LCD_DATA15
| (GPIO) / [[#LCD Interface|LCD D15]]
| 84
| [[#TS-SOCKET|CN1_035]]
| [[#Parallel LCD Interface]], GPIO
| CN1_035
|-
|-
| 2
| 21
| UART7_TXD
| UART7_TXD
| LCD_DATA16
| ([[#UARTs|UART]]) / GPIO
| 85
| [[#Crossbar|FPGA Crossbar]]
| [[#COM_Ports]]
| [[#FPGA|FPGA Crossbar]] (Default CN2_86)
|-
|-
| 2
| 22
| UART7_RXD
| UART7_RXD
| LCD_DATA17
| ([[#UARTs|UART]]) / GPIO
| 86
| [[#Crossbar|FPGA Crossbar]]
| [[#COM_Ports]]
| [[#FPGA|FPGA Crossbar]] (Default CN2_88)
|-
|-
| 2
| 23
| LCD_D18
| LCD_D18
| LCD_DATA18
| (GPIO) / [[#LCD Interface|LCD D18]]
| 87
| [[#TS-SOCKET|CN1_041]]
| [[#Parallel LCD Interface]], GPIO
| CN1_041
|-
|-
| 2
| 24
| LCD_D19
| LCD_D19
| LCD_DATA19
| (GPIO) / [[#LCD Interface|LCD D19]]
| 88
| [[#TS-SOCKET|CN1_043]]
| [[#Parallel LCD Interface]], GPIO
| CN1_043
|-
|-
| 2
| 25
| LCD_D20
| LCD_D20
| LCD_DATA20
| (GPIO) / [[#LCD Interface|LCD D20]]
| 89
| [[#TS-SOCKET|CN1_045]]
| [[#Parallel LCD Interface]], GPIO
| CN1_045
|-
|-
| 2
| 26
| LCD_D21
| LCD_D21
| LCD_DATA21
| (GPIO) / [[#LCD Interface|LCD D21]]
| 90
| [[#TS-SOCKET|CN1_042]]
| [[#Parallel LCD Interface]], GPIO
| CN1_042
|-
|-
| 2
| 27
| LCD_D22
| LCD_D22
| LCD_DATA22
| (GPIO) / [[#LCD Interface|LCD D22]]
| 91
| [[#TS-SOCKET|CN1_044]]
| [[#Parallel LCD Interface]], GPIO
| CN1_044
|-
|-
| 2
| 28
| LCD_D23
| LCD_D23
| LCD_DATA23
| (GPIO) / [[#LCD Interface|LCD D23]]
| 92
| [[#TS-SOCKET|CN1_046]]
| [[#Parallel LCD Interface]], GPIO
| CN1_046
|-
|-
| LCD_PIX_CLK
| 3
| LCD_CLK
| 10
| 64
| SPI_3_OFF_BD_CS#
| [[#Parallel LCD Interface]], GPIO
| ([[#SPI|SPI]]) / GPIO
| CN1_049
| [[#TS-SOCKET|CN2_065]] / [[#HD1_Pin_Header|HD1_13]]
|-
| LCD_DE
| LCD_ENABLE
| 65
| [[#Parallel LCD Interface]], GPIO
| CN1_055
|-
| LCD_HSYNC
| LCD_HSYNC
| 66
| [[#Parallel LCD Interface]], GPIO
| CN1_051
|-
| LCD_VSYNC
| LCD_VSYNC
| 67
| [[#Parallel LCD Interface]], GPIO
| CN1_053
|-
|-
| 3
| 11
| FPGA_RESET#
| FPGA_RESET#
| NAND_WP_B
| (GPIO)
| 107
| [[#FPGA|FPGA]]
| Used to reset on reload
| Onboard FPGA
|-
|-
| 3
| 12
| SPI_3_FPGA_CS#
| SPI_3_FPGA_CS#
| NAND_READY_B
| ([[#SPI|SPI]]) / GPIO
| 108
| [[#FPGA|FPGA]]
| [[#SPI|FPGA SPI CS]]
| Onboard FPGA
|-
|-
| 3
| 13
| SPI_3_CLK
| SPI_3_CLK
| NAND_CE0_B
| ([[#SPI|SPI]]) / GPIO
| 109
| [[#TS-SOCKET|CN2_071]] / [[#HD1_Pin_Header|HD1_15]] / [[#FPGA|FPGA]]
| [[#SPI]]
| CN2_071, HD1 pin 15
|-
|-
| 3
| 14
| SPI_3_MOSI
| SPI_3_MOSI
| NAND_CE1_B
| ([[#SPI|SPI]]) / GPIO
| 110
| [[#TS-SOCKET|CN2_067]] / [[#HD1_Pin_Header|HD1_11]] / [[#FPGA|FPGA]]
| [[#SPI]]
| CN2_067, HD1 pin 11
|-
|-
| 3
| 15
| SPI_3_MISO
| SPI_3_MISO
| NAND_CLE
| ([[#SPI|SPI]]) / GPIO
| 111
| [[#TS-SOCKET|CN2_069]] / [[#HD1_Pin_Header|HD1_9]] / [[#FPGA|FPGA]]
| [[#SPI]]
| CN2_069, HD1 pin 9
|-
|-
| 3
| 16
| SPARE_3
| SPARE_3
| NAND_DQS
| (GPIO)
| 112
| [[#Crossbar|FPGA Crossbar]]
| GPIO
|-
| [[#FPGA|FPGA Crossbar]] (Default NC)
| 3
| 17
| CAM_MCLK
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_034]]
|-
| 3
| 18
| CAM_PIX_CLK
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_032]]
|-
| 3
| 19
| CAM_VSYNC
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_072]]
|-
| 3
| 20
| CAM_HSYNC
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_070]]
|-
| 3
| 21
| CAM_D_0
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_052]]
|-
| 3
| 22
| CAM_D_1
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_056]]
|-
| 3
| 23
| CAM_D_2
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_058]]
|-
|-
| SPI_3_OFF_BD_CS#
| 3
| NAND_ALE
| 24
| 106
| CAM_D_3
| [[#SPI]]
| (GPIO) / Camera Interface
| CN2_065, HD1 pin 13
| [[#TS-SOCKET|CN2_060]]
|-
| 3
| 25
| CAM_D_4
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_062]]
|-
| 3
| 26
| CAM_D_5
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_064]]
|-
| 3
| 27
| CAM_D_6
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_066]]
|-
| 3
| 28
| CAM_D_7
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_068]]
|-
| 4
| 0
| POWER_FAIL
| Power Notification <ref>This will assert high when external power is disconnected.</ref>
| N/A
|-
| 4
| 1
| FPGA_IRQ
| [[#ZPU|ZPU IRQ]]
| [[#FPGA|FPGA]]
|-
| 4
| 8
| SPARE_4
| ([[#Wi-Fi|Wi-Fi IRQ]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
|}
|}


<References />
<References />

Revision as of 14:07, 24 June 2019

The GPIO numbers in the table below are relevant to how the Linux references these numbers. The CPU documentation refers to bank and IO while Linux flattens this out to one number space.

Chip Pin Name Functions [1] Location
0 0 USB_OTG1_ID (USB1 OTG ID) / GPIO CN2_074
0 1 GPIO_1_ADC (GPIO) / ADC input CN2_012
0 8 LCD_PWM_ADC8 (PWM) / ADC input / GPIO CN1_057
0 9 GPIO_9_ADC (PWM) / ADC input / GPIO CN2_091
0 10 EN_ETH_PHY_PWR (Ethernet PHY power en.) / GPIO CN2_046
0 11 AUD_MCLK (I2S Master Clock) / GPIO CN2_054
0 12 AUD_FRM (I2S TX Sync) / GPIO CN2_038
0 13 AUD_CLK (I2S TX Bit Clock) / GPIO CN2_036
0 14 AUD_RXD (I2S RX Data) / GPIO CN2_042
0 15 AUD_TXD (I2S TX Data) / GPIO CN2_040
0 16 CONSOLE_TXD (Console UART) / GPIO CN2_093 / Microcontroller
0 17 CONSOLE_RXD (Console UART) / GPIO CN2_095 / Microcontroller
0 18 SPARE_1 (GPIO) FPGA Crossbar
0 19 SPARE_2 (GPIO) FPGA Crossbar
0 20 UART2_TXD (UART) / GPIO CN2_082
0 21 UART2_RXD (UART) / GPIO CN2_084
0 22 CAN_2_TXD (CAN TX) / GPIO CN1_071
0 23 CAN_2_RXD (CAN RX) / GPIO CN1_069
0 24 UART3_TXD (UART) / GPIO FPGA Crossbar
0 25 UART3_RXD (UART) / GPIO FPGA Crossbar
0 26 UART3_CTS (UART) / GPIO FPGA Crossbar
0 27 UART3_RTS (UART) / GPIO FPGA Crossbar
0 28 UART4_TXD (UART) / GPIO FPGA Crossbar
0 29 UART4_RXD (UART) / GPIO FPGA Crossbar
0 30 UART5_TXD (UART) / GPIO CN2_090
0 31 UART5_RXD (UART) / GPIO CN2_092
2 0 LCD_PIX_CLK (GPIO) / LCD CLK CN1_049
2 1 LCD_DE (GPIO) / LCD DE CN1_055
2 2 LCD_HSYNC (GPIO) / LCD HSYNC CN1_051
2 3 LCD_VSYNC (GPIO) / LCD VSYNC CN1_053
2 7 LCD_D02 (GPIO) / LCD D02 CN1_028
2 8 LCD_D03 (GPIO) / LCD D03 CN1_030
2 9 LCD_D04 (GPIO) / LCD D04 CN1_032
2 10 LCD_D05 (GPIO) / LCD D05 CN1_034
2 11 LCD_D06 (GPIO) / LCD D06 CN1_038
2 12 LCD_D07 (GPIO) / LCD D07 CN1_040
2 13 CAN_1_TXD (CAN0 TX) / GPIO CN2_097
2 14 CAN_1_RXD (CAN0 RX) / GPIO CN2_099
2 15 LCD_D10 (GPIO) / LCD D10 CN1_023
2 16 LCD_D11 (GPIO) / LCD D11 CN1_025
2 17 LCD_D12 (GPIO) / LCD D12 CN1_027
2 18 LCD_D13 (GPIO) / LCD D13 CN1_031
2 19 LCD_D14 (GPIO) / LCD D14 CN1_033
2 20 LCD_D15 (GPIO) / LCD D15 CN1_035
2 21 UART7_TXD (UART) / GPIO FPGA Crossbar
2 22 UART7_RXD (UART) / GPIO FPGA Crossbar
2 23 LCD_D18 (GPIO) / LCD D18 CN1_041
2 24 LCD_D19 (GPIO) / LCD D19 CN1_043
2 25 LCD_D20 (GPIO) / LCD D20 CN1_045
2 26 LCD_D21 (GPIO) / LCD D21 CN1_042
2 27 LCD_D22 (GPIO) / LCD D22 CN1_044
2 28 LCD_D23 (GPIO) / LCD D23 CN1_046
3 10 SPI_3_OFF_BD_CS# (SPI) / GPIO CN2_065 / HD1_13
3 11 FPGA_RESET# (GPIO) FPGA
3 12 SPI_3_FPGA_CS# (SPI) / GPIO FPGA
3 13 SPI_3_CLK (SPI) / GPIO CN2_071 / HD1_15 / FPGA
3 14 SPI_3_MOSI (SPI) / GPIO CN2_067 / HD1_11 / FPGA
3 15 SPI_3_MISO (SPI) / GPIO CN2_069 / HD1_9 / FPGA
3 16 SPARE_3 (GPIO) FPGA Crossbar
3 17 CAM_MCLK (GPIO) / Camera Interface CN2_034
3 18 CAM_PIX_CLK (GPIO) / Camera Interface CN2_032
3 19 CAM_VSYNC (GPIO) / Camera Interface CN2_072
3 20 CAM_HSYNC (GPIO) / Camera Interface CN2_070
3 21 CAM_D_0 (GPIO) / Camera Interface CN2_052
3 22 CAM_D_1 (GPIO) / Camera Interface CN2_056
3 23 CAM_D_2 (GPIO) / Camera Interface CN2_058
3 24 CAM_D_3 (GPIO) / Camera Interface CN2_060
3 25 CAM_D_4 (GPIO) / Camera Interface CN2_062
3 26 CAM_D_5 (GPIO) / Camera Interface CN2_064
3 27 CAM_D_6 (GPIO) / Camera Interface CN2_066
3 28 CAM_D_7 (GPIO) / Camera Interface CN2_068
4 0 POWER_FAIL Power Notification [2] N/A
4 1 FPGA_IRQ ZPU IRQ FPGA
4 8 SPARE_4 (Wi-Fi IRQ) / GPIO FPGA Crossbar
  1. ↑ Common functions for the pin. Default kernel function is denoted with parenthesis "()"
  2. ↑ This will assert high when external power is disconnected.
Retrieved from "http://docs.embeddedTS.com/index.php?title=TS-4100_CPU_DIO_Table&oldid=10579"