TS-4100 CPU DIO Table: Difference between revisions

From embeddedTS Manuals
(Finalized revised CPU GPIO table)
(Remove blurb, move to 4100 toplevel)
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The GPIO numbers in the table below are relevant to how the Linux references these numbers.  The CPU documentation refers to bank and IO while Linux flattens this out to one number space. 
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Revision as of 14:23, 24 June 2019

Chip Pin Name Functions [1] Location
0 0 USB_OTG1_ID (USB1 OTG ID) / GPIO CN2_074
0 1 GPIO_1_ADC (GPIO) / ADC input CN2_012
0 8 LCD_PWM_ADC8 (PWM) / ADC input / GPIO CN1_057
0 9 GPIO_9_ADC (PWM) / ADC input / GPIO CN2_091
0 10 EN_ETH_PHY_PWR (Ethernet PHY power en.) / GPIO CN2_046
0 11 AUD_MCLK (I2S Master Clock) / GPIO CN2_054
0 12 AUD_FRM (I2S TX Sync) / GPIO CN2_038
0 13 AUD_CLK (I2S TX Bit Clock) / GPIO CN2_036
0 14 AUD_RXD (I2S RX Data) / GPIO CN2_042
0 15 AUD_TXD (I2S TX Data) / GPIO CN2_040
0 16 CONSOLE_TXD (Console UART) / GPIO CN2_093 / Microcontroller
0 17 CONSOLE_RXD (Console UART) / GPIO CN2_095 / Microcontroller
0 18 SPARE_1 (GPIO) FPGA Crossbar
0 19 SPARE_2 (GPIO) FPGA Crossbar
0 20 UART2_TXD (UART) / GPIO CN2_082
0 21 UART2_RXD (UART) / GPIO CN2_084
0 22 CAN_2_TXD (CAN TX) / GPIO CN1_071
0 23 CAN_2_RXD (CAN RX) / GPIO CN1_069
0 24 UART3_TXD (UART) / GPIO FPGA Crossbar
0 25 UART3_RXD (UART) / GPIO FPGA Crossbar
0 26 UART3_CTS (UART) / GPIO FPGA Crossbar
0 27 UART3_RTS (UART) / GPIO FPGA Crossbar
0 28 UART4_TXD (UART) / GPIO FPGA Crossbar
0 29 UART4_RXD (UART) / GPIO FPGA Crossbar
0 30 UART5_TXD (UART) / GPIO CN2_090
0 31 UART5_RXD (UART) / GPIO CN2_092
2 0 LCD_PIX_CLK (GPIO) / LCD CLK CN1_049
2 1 LCD_DE (GPIO) / LCD DE CN1_055
2 2 LCD_HSYNC (GPIO) / LCD HSYNC CN1_051
2 3 LCD_VSYNC (GPIO) / LCD VSYNC CN1_053
2 7 LCD_D02 (GPIO) / LCD D02 CN1_028
2 8 LCD_D03 (GPIO) / LCD D03 CN1_030
2 9 LCD_D04 (GPIO) / LCD D04 CN1_032
2 10 LCD_D05 (GPIO) / LCD D05 CN1_034
2 11 LCD_D06 (GPIO) / LCD D06 CN1_038
2 12 LCD_D07 (GPIO) / LCD D07 CN1_040
2 13 CAN_1_TXD (CAN0 TX) / GPIO CN2_097
2 14 CAN_1_RXD (CAN0 RX) / GPIO CN2_099
2 15 LCD_D10 (GPIO) / LCD D10 CN1_023
2 16 LCD_D11 (GPIO) / LCD D11 CN1_025
2 17 LCD_D12 (GPIO) / LCD D12 CN1_027
2 18 LCD_D13 (GPIO) / LCD D13 CN1_031
2 19 LCD_D14 (GPIO) / LCD D14 CN1_033
2 20 LCD_D15 (GPIO) / LCD D15 CN1_035
2 21 UART7_TXD (UART) / GPIO FPGA Crossbar
2 22 UART7_RXD (UART) / GPIO FPGA Crossbar
2 23 LCD_D18 (GPIO) / LCD D18 CN1_041
2 24 LCD_D19 (GPIO) / LCD D19 CN1_043
2 25 LCD_D20 (GPIO) / LCD D20 CN1_045
2 26 LCD_D21 (GPIO) / LCD D21 CN1_042
2 27 LCD_D22 (GPIO) / LCD D22 CN1_044
2 28 LCD_D23 (GPIO) / LCD D23 CN1_046
3 10 SPI_3_OFF_BD_CS# (SPI) / GPIO CN2_065 / HD1_13
3 11 FPGA_RESET# (GPIO) FPGA
3 12 SPI_3_FPGA_CS# (SPI) / GPIO FPGA
3 13 SPI_3_CLK (SPI) / GPIO CN2_071 / HD1_15 / FPGA
3 14 SPI_3_MOSI (SPI) / GPIO CN2_067 / HD1_11 / FPGA
3 15 SPI_3_MISO (SPI) / GPIO CN2_069 / HD1_9 / FPGA
3 16 SPARE_3 (GPIO) FPGA Crossbar
3 17 CAM_MCLK (GPIO) / Camera Interface CN2_034
3 18 CAM_PIX_CLK (GPIO) / Camera Interface CN2_032
3 19 CAM_VSYNC (GPIO) / Camera Interface CN2_072
3 20 CAM_HSYNC (GPIO) / Camera Interface CN2_070
3 21 CAM_D_0 (GPIO) / Camera Interface CN2_052
3 22 CAM_D_1 (GPIO) / Camera Interface CN2_056
3 23 CAM_D_2 (GPIO) / Camera Interface CN2_058
3 24 CAM_D_3 (GPIO) / Camera Interface CN2_060
3 25 CAM_D_4 (GPIO) / Camera Interface CN2_062
3 26 CAM_D_5 (GPIO) / Camera Interface CN2_064
3 27 CAM_D_6 (GPIO) / Camera Interface CN2_066
3 28 CAM_D_7 (GPIO) / Camera Interface CN2_068
4 0 POWER_FAIL Power Notification [2] N/A
4 1 FPGA_IRQ ZPU IRQ FPGA
4 8 SPARE_4 (Wi-Fi IRQ) / GPIO FPGA Crossbar
  1. ↑ Common functions for the pin. Default kernel function is denoted with parenthesis "()"
  2. ↑ This will assert high when external power is disconnected.
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