TS-4100 CPU DIO Table: Difference between revisions

From embeddedTS Manuals
(Partial convert to chip/bank notation for new character GPIO interface)
(Fixed I2S links)
 
(4 intermediate revisions by the same user not shown)
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The GPIO numbers in the table below are relevant to how the Linux references these numbers.  The CPU documentation refers to bank and IO while Linux flattens this out to one number space. 
{| class="wikitable sortable"
{| class="wikitable sortable"
|-
|-
! Chip
! Chip
! Pin
! Pin
! Name
! Functions
! REMOVE
! Functions <ref>Common functions for the pin. Default kernel function is denoted with parenthesis "()"</ref>
! Location
! Location
|-
|-
| 0
| 0
| 0
| 0
| USB_OTG1_ID
|
| ([[#USB|USB1 OTG ID]]) / GPIO
| ([[#USB|USB1 OTG ID]]) / GPIO
| [[#TS-SOCKET|CN2_074]]
| [[#TS-SOCKET|CN2_074]]
Line 19: Line 13:
| 0
| 0
| 1
| 1
| GPIO_1_ADC
|
| (GPIO) / [[#ADC|ADC input]]
| (GPIO) / [[#ADC|ADC input]]
| [[#TS-SOCKET|CN2_012]]
| [[#TS-SOCKET|CN2_012]]
Line 26: Line 18:
| 0
| 0
| 8
| 8
| LCD_PWM_ADC8
| ([[#PWM|PWM0]]) / [[#ADC|ADC input]] / GPIO
|
| ([[#PWM|PWM]]) / [[#ADC|ADC input]] / GPIO
| [[#TS-SOCKET|CN1_057]]
| [[#TS-SOCKET|CN1_057]]
|-
|-
| 0
| 0
| 9
| 9
| GPIO_9_ADC
| ([[#PWM|PWM1]]) / [[#ADC|ADC input]] / GPIO
|
| ([[#PWM|PWM]]) / [[#ADC|ADC input]] / GPIO
| [[#TS-SOCKET|CN2_091]]
| [[#TS-SOCKET|CN2_091]]
|-
|-
| 0
| 0
| 10
| 10
| EN_ETH_PHY_PWR
|
| ([[#Ethernet|Ethernet PHY power en.]]) / GPIO
| ([[#Ethernet|Ethernet PHY power en.]]) / GPIO
| [[#TS-SOCKET|CN2_046]]
| [[#TS-SOCKET|CN2_046]]
Line 47: Line 33:
|0
|0
| 11
| 11
| AUD_MCLK
| ([[#I2S_Audio|I2S Master Clock]]) / GPIO
|
| ([[#I2S|I2S Master Clock]]) / GPIO
| [[#TS-SOCKET|CN2_054]]
| [[#TS-SOCKET|CN2_054]]
|-
|-
| 0
| 0
| 12
| 12
| AUD_FRM
| ([[#I2S_Audio|I2S TX Sync]]) / GPIO
|
| ([[#I2S|I2S TX Sync]]) / GPIO
| [[#TS-SOCKET|CN2_038]]
| [[#TS-SOCKET|CN2_038]]
|-
|-
| 0
| 0
| 13
| 13
| AUD_CLK
| ([[#I2S_Audio|I2S TX Bit Clock]]) / GPIO
|
| ([[#I2S|I2S TX Bit Clock]]) / GPIO
| [[#TS-SOCKET|CN2_036]]
| [[#TS-SOCKET|CN2_036]]
|-
|-
| 0
| 0
| 14
| 14
| AUD_RXD
| ([[#I2S_Audio|I2S RX Data]]) / GPIO
|
| ([[#I2S|I2S RX Data]]) / GPIO
| [[#TS-SOCKET|CN2_042]]
| [[#TS-SOCKET|CN2_042]]
|-
|-
| 0
| 0
| 15
| 15
| AUD_TXD
| ([[#I2S_Audio|I2S TX Data]]) / GPIO
|
| ([[#I2S|I2S TX Data]]) / GPIO
| [[#TS-SOCKET|CN2_040]]
| [[#TS-SOCKET|CN2_040]]
|-
|-
| 0
| 0
| 16
| 16
| CONSOLE_TXD
| ([[#UARTs|Console UART TXD]]) / GPIO
|
| ([[#UARTs|Console UART]]) / GPIO
| [[#TS-SOCKET|CN2_093]] / [[#Supervisory Microcontroller|Microcontroller]]
| [[#TS-SOCKET|CN2_093]] / [[#Supervisory Microcontroller|Microcontroller]]
|-
|-
| 0
| 0
| 17
| 17
| CONSOLE_RXD
| ([[#UARTs|Console UART RXD]]) / GPIO
|
| ([[#UARTs|Console UART]]) / GPIO
| [[#TS-SOCKET|CN2_095]] / [[#Supervisory Microcontroller|Microcontroller]]
| [[#TS-SOCKET|CN2_095]] / [[#Supervisory Microcontroller|Microcontroller]]
|-
|-
| 0
| 0
| 18
| 18
| SPARE_1
|
| (GPIO)
| (GPIO)
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar SPARE_1]]
|-
|-
| 0
| 0
| 19
| 19
| SPARE_2
|
| (GPIO)
| (GPIO)
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar SPARE_2]]
|-
|-
| 0
| 0
| 20
| 20
| UART2_TXD
| ([[#UARTs|UART1 TXD]]) / GPIO
|
| ([[#UARTs|UART]]) / GPIO
| [[#TS-SOCKET|CN2_082]]
| [[#TS-SOCKET|CN2_082]]
|-
|-
| 0
| 0
| 21
| 21
| UART2_RXD
| ([[#UARTs|UART1 RXD]]) / GPIO
|
| ([[#UARTs|UART]]) / GPIO
| [[#TS-SOCKET|CN2_084]]
| [[#TS-SOCKET|CN2_084]]
|-
|-
| 0
| 0
| 22
| 22
| CAN_2_TXD
| ([[#CAN|CAN1 TX]]) / GPIO
|
| ([[#CAN|CAN TX]]) / GPIO
| [[#TS-SOCKET|CN1_071]]
| [[#TS-SOCKET|CN1_071]]
|-
|-
| 0
| 0
| 23
| 23
| CAN_2_RXD
| ([[#CAN|CAN1 RX]]) / GPIO
|
| ([[#CAN|CAN RX]]) / GPIO
| [[#TS-SOCKET|CN1_069]]
| [[#TS-SOCKET|CN1_069]]
|-
|-
| 0
| 0
| 24
| 24
| UART3_TXD
| ([[#UARTs|UART2 TXD]]) / GPIO
|
| [[#Crossbar|FPGA Crossbar UART2_TXD]]
| ([[#UARTs|UART3 TX]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 25
| 25
| UART3_RXD
| ([[#UARTs|UART2 RXD]]) / GPIO
|
| [[#Crossbar|FPGA Crossbar UART2_RXD]]
| ([[#UARTs|UART3 RX]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 26
| 26
| UART3_CTS
| ([[#UARTs|UART2 CTS]]) / GPIO
|
| [[#Crossbar|FPGA Crossbar UART2_CTS]]
| ([[#UARTs|UART3 CTS]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 27
| 27
| UART3_RTS
| ([[#UARTs|UART2 RTS]]) / GPIO
|
| [[#Crossbar|FPGA Crossbar UART2_RTS]]  
| ([[#UARTs|UART3 RTS]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]  
|-
|-
| 0
| 0
| 28
| 28
| UART4_TXD
| ([[#UARTs|UART3 TXD]]) / GPIO
|
| [[#Crossbar|FPGA Crossbar UART3_TXD]]
| ([[#UARTs|UART4 TX]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 29
| 29
| UART4_RXD
| ([[#UARTs|UART3 RXD]]) / GPIO
|
| [[#Crossbar|FPGA Crossbar UART3_RXD]]
| ([[#UARTs|UART4 RX]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 30
| 30
| UART5_TXD
| ([[#UARTs|UART4 TXD]]) / GPIO
|
| ([[#UARTs|UART5 TX]]) / GPIO
| [[#TS-SOCKET|CN2_090]]
| [[#TS-SOCKET|CN2_090]]
|-
|-
| 0
| 0
| 31
| 31
| UART5_RXD
| ([[#UARTs|UART4 RXD]]) / GPIO
|
| ([[#UARTs|UART5 RX]]) / GPIO
| [[#TS-SOCKET|CN2_092]]
| [[#TS-SOCKET|CN2_092]]
|-
|-
| CAM_D_0
| 2
| CSI_DATA00
| 0
| 117
| (GPIO) / [[#LCD Interface|LCD CLK]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_049]]
| CN2_052
|-
|-
| CAM_D_1
| 2
| CSI_DATA01
| 1
| 118
| (GPIO) / [[#LCD Interface|LCD DE]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_055]]
| CN2_056
|-
|-
| CAM_D_2
| 2
| CSI_DATA02
| 2
| 119
| (GPIO) / [[#LCD Interface|LCD HSYNC]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_051]]
| CN2_058
|-
|-
| CAM_D_3
| 2
| CSI_DATA03
| 3
| 120
| (GPIO) / [[#LCD Interface|LCD VSYNC]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_053]]
| CN2_060
|-
|-
| CAM_D_4
| 2
| CSI_DATA04
| 7
| 121
| (GPIO) / [[#LCD Interface|LCD D02]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_028]]
| CN2_062
|-
|-
| CAM_D_5
| 2
| CSI_DATA05
| 8
| 122
| (GPIO) / [[#LCD Interface|LCD D03]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_030]]
| CN2_064
|-
|-
| CAM_D_6
| 2
| CSI_DATA06
| 9
| 123
| (GPIO) / [[#LCD Interface|LCD D04]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_032]]
| CN2_066
|-
|-
| CAM_D_7
| 2
| CSI_DATA07
| 10
| 124
| (GPIO) / [[#LCD Interface|LCD D05]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_034]]
| CN2_068
|-
|-
| CAM_HSYNC
| 2
| CSI_HSYNC
| 11
| 116
| (GPIO) / [[#LCD Interface|LCD D06]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_038]]
| CN2_070
|-
|-
| CAM_MCLK
| 2
| CSI_MCLK
| 12
| 113
| (GPIO) / [[#LCD Interface|LCD D07]]
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN1_040]]
| CN2_034
|-
|-
| CAM_PIX_CLK
| 2
| CSI_PIXCLK
| 13
| 114
| ([[#CAN|CAN0 TX]]) / GPIO
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_097]]
| CN2_032
|-
|-
| CAM_VSYNC
| 2
| CSI_VSYNC
| 14
| 115
| ([[#CAN|CAN0 RX]]) / GPIO
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_099]]
| CN2_072
|-
|-
| POWER_FAIL
| 2
| SNVS_TAMPER0
| 15
| 128
| (GPIO) / [[#LCD Interface|LCD D10]]
| Power Notification <ref>This will assert high when power is disconnected and the system and the board is running off supercaps if populated.</ref>
| [[#TS-SOCKET|CN1_023]]
| Onboard PWR Monitor
|-
|-
| FPGA_IRQ
| 2
| SNVS_TAMPER1
| 16
| 129
| (GPIO) / [[#LCD Interface|LCD D11]]
| [[#FPGA]]
| [[#TS-SOCKET|CN1_025]]
| [[#FPGA|FPGA Crossbar]] (Default NC)
|-
|-
| EN_FPGA_PWR
| 2
| SNVS_TAMPER2
| 17
| 130
| (GPIO) / [[#LCD Interface|LCD D12]]
| FPGA 3.3V switch
| [[#TS-SOCKET|CN1_027]]
| Onboard FET
|-
|-
| GPIO_DVFS
| 2
| SNVS_TAMPER3
| 18
| 131
| (GPIO) / [[#LCD Interface|LCD D13]]
| CPU DVFS <ref>Under almost all cases this should be maintained by the kernel</ref>
| [[#TS-SOCKET|CN1_031]]
| Onboard Regulator
|-
|-
| JTAG_FPGA_TDO
| 2
| SNVS_TAMPER4
| 19
| 132
| (GPIO) / [[#LCD Interface|LCD D14]]
| FPGA JTAG
| [[#TS-SOCKET|CN1_033]]
| [[#FPGA|FPGA JTAG pin]]
|-
|-
| JTAG_FPGA_TDI
| 2
| SNVS_TAMPER5
| 20
| 133
| (GPIO) / [[#LCD Interface|LCD D15]]
| FPGA JTAG
| [[#TS-SOCKET|CN1_035]]
| [[#FPGA|FPGA JTAG pin]]
|-
|-
| JTAG_FPGA_TMS
| 2
| SNVS_TAMPER6
| 21
| 134
| ([[#UARTs|UART6 TXD]]) / GPIO
| FPGA JTAG
| [[#Crossbar|FPGA Crossbar UART6_TXD]]
| [[#FPGA|FPGA JTAG pin]]
|-
|-
| JTAG_FPGA_TCK
| 2
| SNVS_TAMPER7
| 22
| 135
| ([[#UARTs|UART6 RXD]]) / GPIO
| FPGA JTAG
| [[#Crossbar|FPGA Crossbar UART6_RXD]]
| [[#FPGA|FPGA JTAG pin]]
|-
|-
| SPARE_4
| 2
| SNVS_TAMPER8
| 23
| 136
| ([[#PWM|PWM4]]) / GPIO / [[#LCD Interface|LCD D18]]
| GPIO
| [[#TS-SOCKET|CN1_041]]
| [[#FPGA|FPGA Crossbar]] (Default WIFI IRQ)
|-
|-
| EN_SD_POWER
| 2
| SNVS_TAMPER9
| 24
| 137
| ([[#PWM|PWM5]]) / GPIO / [[#LCD Interface|LCD D19]]
| SD power enable
| [[#TS-SOCKET|CN1_043]]
| Onboard Regulator
|-
|-
| I2C_3_DAT
| 2
| LCD_DATA00
| 25
| 69
| (GPIO) / [[#LCD Interface|LCD D20]]
| [[#I2C]] <ref name=fpgaio>This i2c bus is used to access all of the FPGA GPIO and typically should not be repurposed as GPIO.</ref>
| [[#TS-SOCKET|CN1_045]]
| CN2_030, HD1 pin 10
|-
|-
| I2C_3_CLK
| 2
| LCD_DATA01
| 26
| 70
| (GPIO) / [[#LCD Interface|LCD D21]]
| [[#I2C]] <ref name=fpgaio />
| [[#TS-SOCKET|CN1_042]]
| CN2_028, HD1 pin 8
|-
|-
| LCD_D02
| 2
| LCD_DATA02
| 27
| 71
| (GPIO) / [[#LCD Interface|LCD D22]]
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN1_044]]
| CN1_028
|-
|-
| LCD_D03
| 2
| LCD_DATA03
| 28
| 72
| (GPIO) / [[#LCD Interface|LCD D23]]
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN1_046]]
| CN1_030
|-
|-
| LCD_D04
| 3
| LCD_DATA04
| 10
| 73
| ([[#SPI|SPI2 Offboard CS#]]) / GPIO
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_065]] / [[#HD1_Pin_Header|HD1_13]]
| CN1_032
|-
|-
| LCD_D05
| 3
| LCD_DATA05
| 11
| 74
| (GPIO)
| [[#Parallel LCD Interface]], GPIO
| [[#FPGA|FPGA_RESET#]]
| CN1_034
|-
|-
| LCD_D06
| 3
| LCD_DATA06
| 12
| 75
| ([[#SPI|SPI2 FPGA CS#]]) / GPIO
| [[#Parallel LCD Interface]], GPIO
| [[#FPGA|FPGA]]
| CN1_038
|-
|-
| LCD_D07
| 3
| LCD_DATA07
| 13
| 76
| ([[#SPI|SPI2 CLK]]) / GPIO
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_071]] / [[#HD1_Pin_Header|HD1_15]] / [[#FPGA|FPGA]]
| CN1_040
|-
|-
| CAN_1_TXD
| 3
| LCD_DATA08
| 14
| 77
| ([[#SPI|SPI2 MOSI]]) / GPIO
| [[#CAN]], GPIO
| [[#TS-SOCKET|CN2_067]] / [[#HD1_Pin_Header|HD1_11]] / [[#FPGA|FPGA]]
| CN2_097
|-
|-
| CAN_1_RXD
| 3
| LCD_DATA09
| 15
| 78
| ([[#SPI|SPI2 MISO]]) / GPIO
| [[#CAN]], GPIO
| [[#TS-SOCKET|CN2_069]] / [[#HD1_Pin_Header|HD1_9]] / [[#FPGA|FPGA]]
| CN2_099
|-
|-
| LCD_D10
| 3
| LCD_DATA10
| 16
| 79
| (GPIO)
| [[#Parallel LCD Interface]], GPIO
| [[#Crossbar|FPGA Crossbar SPARE_3]]
| CN1_023
|-
|-
| LCD_D11
| 3
| LCD_DATA11
| 17
| 80
| (GPIO) / Camera MCLK
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_034]]
| CN1_025
|-
|-
| LCD_D12
| 3
| LCD_DATA12
| 18
| 81
| (GPIO) / Camera PIXCLK
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_032]]
| CN1_027
|-
|-
| LCD_D13
| 3
| LCD_DATA13
| 19
| 82
| (GPIO) / Camera VSYNC
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_072]]
| CN1_031
|-
|-
| LCD_D14
| 3
| LCD_DATA14
| 20
| 83
| (GPIO) / Camera HSYNC
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_070]]
| CN1_033
|-
|-
| LCD_D15
| 3
| LCD_DATA15
| 21
| 84
| (GPIO) / Camera D0
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_052]]
| CN1_035
|-
|-
| UART7_TXD
| 3
| LCD_DATA16
| 22
| 85
| (GPIO) / Camera D1
| [[#COM_Ports]]
| [[#TS-SOCKET|CN2_056]]
| [[#FPGA|FPGA Crossbar]] (Default CN2_86)
|-
|-
| UART7_RXD
| 3
| LCD_DATA17
| 23
| 86
| (GPIO) / Camera D2
| [[#COM_Ports]]
| [[#TS-SOCKET|CN2_058]]
| [[#FPGA|FPGA Crossbar]] (Default CN2_88)
|-
|-
| LCD_D18
| 3
| LCD_DATA18
| 24
| 87
| (GPIO) / Camera D3
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_060]]
| CN1_041
|-
|-
| LCD_D19
| 3
| LCD_DATA19
| 25
| 88
| (GPIO) / Camera D4
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_062]]
| CN1_043
|-
|-
| LCD_D20
| 3
| LCD_DATA20
| 26
| 89
| (GPIO) / Camera D5
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_064]]
| CN1_045
|-
|-
| LCD_D21
| 3
| LCD_DATA21
| 27
| 90
| (GPIO) / Camera D6
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_066]]
| CN1_042
|-
|-
| LCD_D22
| 3
| LCD_DATA22
| 28
| 91
| (GPIO) / Camera D7
| [[#Parallel LCD Interface]], GPIO
| [[#TS-SOCKET|CN2_068]]
| CN1_044
|-
|-
| LCD_D23
| 4
| LCD_DATA23
| 0
| 92
| POWER_FAIL<ref>Asserted when external power input falls below valid input range.</ref>
| [[#Parallel LCD Interface]], GPIO
| N/A
| CN1_046
|-
|-
| LCD_PIX_CLK
| 4
| LCD_CLK
| 1
| 64
| [[#ZPU|ZPU IRQ]]
| [[#Parallel LCD Interface]], GPIO
| [[#FPGA|FPGA]]
| CN1_049
|-
|-
| LCD_DE
| 4
| LCD_ENABLE
| 8
| 65
| ([[#Wi-Fi|Wi-Fi IRQ]]) / GPIO
| [[#Parallel LCD Interface]], GPIO
| [[#Crossbar|FPGA Crossbar SPARE_4]]
| CN1_055
|-
| LCD_HSYNC
| LCD_HSYNC
| 66
| [[#Parallel LCD Interface]], GPIO
| CN1_051
|-
| LCD_VSYNC
| LCD_VSYNC
| 67
| [[#Parallel LCD Interface]], GPIO
| CN1_053
|-
| FPGA_RESET#
| NAND_WP_B
| 107
| Used to reset on reload
| Onboard FPGA
|-
| SPI_3_FPGA_CS#
| NAND_READY_B
| 108
| [[#SPI|FPGA SPI CS]]
| Onboard FPGA
|-
| SPI_3_CLK
| NAND_CE0_B
| 109
| [[#SPI]]
| CN2_071, HD1 pin 15
|-
| SPI_3_MOSI
| NAND_CE1_B
| 110
| [[#SPI]]
| CN2_067, HD1 pin 11
|-
| SPI_3_MISO
| NAND_CLE
| 111
| [[#SPI]]
| CN2_069, HD1 pin 9
|-
| SPARE_3
| NAND_DQS
| 112
| GPIO
| [[#FPGA|FPGA Crossbar]] (Default NC)
|-
| SPI_3_OFF_BD_CS#
| NAND_ALE
| 106
| [[#SPI]]
| CN2_065, HD1 pin 13
|}
|}


<References />
<references/>

Latest revision as of 17:12, 26 July 2019

Chip Pin Functions Location
0 0 (USB1 OTG ID) / GPIO CN2_074
0 1 (GPIO) / ADC input CN2_012
0 8 (PWM0) / ADC input / GPIO CN1_057
0 9 (PWM1) / ADC input / GPIO CN2_091
0 10 (Ethernet PHY power en.) / GPIO CN2_046
0 11 (I2S Master Clock) / GPIO CN2_054
0 12 (I2S TX Sync) / GPIO CN2_038
0 13 (I2S TX Bit Clock) / GPIO CN2_036
0 14 (I2S RX Data) / GPIO CN2_042
0 15 (I2S TX Data) / GPIO CN2_040
0 16 (Console UART TXD) / GPIO CN2_093 / Microcontroller
0 17 (Console UART RXD) / GPIO CN2_095 / Microcontroller
0 18 (GPIO) FPGA Crossbar SPARE_1
0 19 (GPIO) FPGA Crossbar SPARE_2
0 20 (UART1 TXD) / GPIO CN2_082
0 21 (UART1 RXD) / GPIO CN2_084
0 22 (CAN1 TX) / GPIO CN1_071
0 23 (CAN1 RX) / GPIO CN1_069
0 24 (UART2 TXD) / GPIO FPGA Crossbar UART2_TXD
0 25 (UART2 RXD) / GPIO FPGA Crossbar UART2_RXD
0 26 (UART2 CTS) / GPIO FPGA Crossbar UART2_CTS
0 27 (UART2 RTS) / GPIO FPGA Crossbar UART2_RTS
0 28 (UART3 TXD) / GPIO FPGA Crossbar UART3_TXD
0 29 (UART3 RXD) / GPIO FPGA Crossbar UART3_RXD
0 30 (UART4 TXD) / GPIO CN2_090
0 31 (UART4 RXD) / GPIO CN2_092
2 0 (GPIO) / LCD CLK CN1_049
2 1 (GPIO) / LCD DE CN1_055
2 2 (GPIO) / LCD HSYNC CN1_051
2 3 (GPIO) / LCD VSYNC CN1_053
2 7 (GPIO) / LCD D02 CN1_028
2 8 (GPIO) / LCD D03 CN1_030
2 9 (GPIO) / LCD D04 CN1_032
2 10 (GPIO) / LCD D05 CN1_034
2 11 (GPIO) / LCD D06 CN1_038
2 12 (GPIO) / LCD D07 CN1_040
2 13 (CAN0 TX) / GPIO CN2_097
2 14 (CAN0 RX) / GPIO CN2_099
2 15 (GPIO) / LCD D10 CN1_023
2 16 (GPIO) / LCD D11 CN1_025
2 17 (GPIO) / LCD D12 CN1_027
2 18 (GPIO) / LCD D13 CN1_031
2 19 (GPIO) / LCD D14 CN1_033
2 20 (GPIO) / LCD D15 CN1_035
2 21 (UART6 TXD) / GPIO FPGA Crossbar UART6_TXD
2 22 (UART6 RXD) / GPIO FPGA Crossbar UART6_RXD
2 23 (PWM4) / GPIO / LCD D18 CN1_041
2 24 (PWM5) / GPIO / LCD D19 CN1_043
2 25 (GPIO) / LCD D20 CN1_045
2 26 (GPIO) / LCD D21 CN1_042
2 27 (GPIO) / LCD D22 CN1_044
2 28 (GPIO) / LCD D23 CN1_046
3 10 (SPI2 Offboard CS#) / GPIO CN2_065 / HD1_13
3 11 (GPIO) FPGA_RESET#
3 12 (SPI2 FPGA CS#) / GPIO FPGA
3 13 (SPI2 CLK) / GPIO CN2_071 / HD1_15 / FPGA
3 14 (SPI2 MOSI) / GPIO CN2_067 / HD1_11 / FPGA
3 15 (SPI2 MISO) / GPIO CN2_069 / HD1_9 / FPGA
3 16 (GPIO) FPGA Crossbar SPARE_3
3 17 (GPIO) / Camera MCLK CN2_034
3 18 (GPIO) / Camera PIXCLK CN2_032
3 19 (GPIO) / Camera VSYNC CN2_072
3 20 (GPIO) / Camera HSYNC CN2_070
3 21 (GPIO) / Camera D0 CN2_052
3 22 (GPIO) / Camera D1 CN2_056
3 23 (GPIO) / Camera D2 CN2_058
3 24 (GPIO) / Camera D3 CN2_060
3 25 (GPIO) / Camera D4 CN2_062
3 26 (GPIO) / Camera D5 CN2_064
3 27 (GPIO) / Camera D6 CN2_066
3 28 (GPIO) / Camera D7 CN2_068
4 0 POWER_FAIL[1] N/A
4 1 ZPU IRQ FPGA
4 8 (Wi-Fi IRQ) / GPIO FPGA Crossbar SPARE_4
  1. ↑ Asserted when external power input falls below valid input range.
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