TS-4100 CPU DIO Table: Difference between revisions

From embeddedTS Manuals
(Finalized revised CPU GPIO table)
(Fixed I2S links)
 
(3 intermediate revisions by the same user not shown)
Line 1: Line 1:
The GPIO numbers in the table below are relevant to how the Linux references these numbers.  The CPU documentation refers to bank and IO while Linux flattens this out to one number space. 
{| class="wikitable sortable"
{| class="wikitable sortable"
|-
|-
! Chip
! Chip
! Pin
! Pin
! Name
! Functions
 
! Functions <ref>Common functions for the pin. Default kernel function is denoted with parenthesis "()"</ref>
! Location
! Location
|-
|-
| 0
| 0
| 0
| 0
| USB_OTG1_ID
| ([[#USB|USB1 OTG ID]]) / GPIO
| ([[#USB|USB1 OTG ID]]) / GPIO
| [[#TS-SOCKET|CN2_074]]
| [[#TS-SOCKET|CN2_074]]
Line 18: Line 13:
| 0
| 0
| 1
| 1
| GPIO_1_ADC
| (GPIO) / [[#ADC|ADC input]]
| (GPIO) / [[#ADC|ADC input]]
| [[#TS-SOCKET|CN2_012]]
| [[#TS-SOCKET|CN2_012]]
Line 24: Line 18:
| 0
| 0
| 8
| 8
| LCD_PWM_ADC8
| ([[#PWM|PWM0]]) / [[#ADC|ADC input]] / GPIO
| ([[#PWM|PWM]]) / [[#ADC|ADC input]] / GPIO
| [[#TS-SOCKET|CN1_057]]
| [[#TS-SOCKET|CN1_057]]
|-
|-
| 0
| 0
| 9
| 9
| GPIO_9_ADC
| ([[#PWM|PWM1]]) / [[#ADC|ADC input]] / GPIO
| ([[#PWM|PWM]]) / [[#ADC|ADC input]] / GPIO
| [[#TS-SOCKET|CN2_091]]
| [[#TS-SOCKET|CN2_091]]
|-
|-
| 0
| 0
| 10
| 10
| EN_ETH_PHY_PWR
| ([[#Ethernet|Ethernet PHY power en.]]) / GPIO
| ([[#Ethernet|Ethernet PHY power en.]]) / GPIO
| [[#TS-SOCKET|CN2_046]]
| [[#TS-SOCKET|CN2_046]]
Line 42: Line 33:
|0
|0
| 11
| 11
| AUD_MCLK
| ([[#I2S_Audio|I2S Master Clock]]) / GPIO
| ([[#I2S|I2S Master Clock]]) / GPIO
| [[#TS-SOCKET|CN2_054]]
| [[#TS-SOCKET|CN2_054]]
|-
|-
| 0
| 0
| 12
| 12
| AUD_FRM
| ([[#I2S_Audio|I2S TX Sync]]) / GPIO
| ([[#I2S|I2S TX Sync]]) / GPIO
| [[#TS-SOCKET|CN2_038]]
| [[#TS-SOCKET|CN2_038]]
|-
|-
| 0
| 0
| 13
| 13
| AUD_CLK
| ([[#I2S_Audio|I2S TX Bit Clock]]) / GPIO
| ([[#I2S|I2S TX Bit Clock]]) / GPIO
| [[#TS-SOCKET|CN2_036]]
| [[#TS-SOCKET|CN2_036]]
|-
|-
| 0
| 0
| 14
| 14
| AUD_RXD
| ([[#I2S_Audio|I2S RX Data]]) / GPIO
| ([[#I2S|I2S RX Data]]) / GPIO
| [[#TS-SOCKET|CN2_042]]
| [[#TS-SOCKET|CN2_042]]
|-
|-
| 0
| 0
| 15
| 15
| AUD_TXD
| ([[#I2S_Audio|I2S TX Data]]) / GPIO
| ([[#I2S|I2S TX Data]]) / GPIO
| [[#TS-SOCKET|CN2_040]]
| [[#TS-SOCKET|CN2_040]]
|-
|-
| 0
| 0
| 16
| 16
| CONSOLE_TXD
| ([[#UARTs|Console UART TXD]]) / GPIO
| ([[#UARTs|Console UART]]) / GPIO
| [[#TS-SOCKET|CN2_093]] / [[#Supervisory Microcontroller|Microcontroller]]
| [[#TS-SOCKET|CN2_093]] / [[#Supervisory Microcontroller|Microcontroller]]
|-
|-
| 0
| 0
| 17
| 17
| CONSOLE_RXD
| ([[#UARTs|Console UART RXD]]) / GPIO
| ([[#UARTs|Console UART]]) / GPIO
| [[#TS-SOCKET|CN2_095]] / [[#Supervisory Microcontroller|Microcontroller]]
| [[#TS-SOCKET|CN2_095]] / [[#Supervisory Microcontroller|Microcontroller]]
|-
|-
| 0
| 0
| 18
| 18
| SPARE_1
| (GPIO)
| (GPIO)
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar SPARE_1]]
|-
|-
| 0
| 0
| 19
| 19
| SPARE_2
| (GPIO)
| (GPIO)
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar SPARE_2]]
|-
|-
| 0
| 0
| 20
| 20
| UART2_TXD
| ([[#UARTs|UART1 TXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#TS-SOCKET|CN2_082]]
| [[#TS-SOCKET|CN2_082]]
|-
|-
| 0
| 0
| 21
| 21
| UART2_RXD
| ([[#UARTs|UART1 RXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#TS-SOCKET|CN2_084]]
| [[#TS-SOCKET|CN2_084]]
|-
|-
| 0
| 0
| 22
| 22
| CAN_2_TXD
| ([[#CAN|CAN1 TX]]) / GPIO
| ([[#CAN|CAN TX]]) / GPIO
| [[#TS-SOCKET|CN1_071]]
| [[#TS-SOCKET|CN1_071]]
|-
|-
| 0
| 0
| 23
| 23
| CAN_2_RXD
| ([[#CAN|CAN1 RX]]) / GPIO
| ([[#CAN|CAN RX]]) / GPIO
| [[#TS-SOCKET|CN1_069]]
| [[#TS-SOCKET|CN1_069]]
|-
|-
| 0
| 0
| 24
| 24
| UART3_TXD
| ([[#UARTs|UART2 TXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART2_TXD]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 25
| 25
| UART3_RXD
| ([[#UARTs|UART2 RXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART2_RXD]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 26
| 26
| UART3_CTS
| ([[#UARTs|UART2 CTS]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART2_CTS]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 27
| 27
| UART3_RTS
| ([[#UARTs|UART2 RTS]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART2_RTS]]  
| [[#Crossbar|FPGA Crossbar]]  
|-
|-
| 0
| 0
| 28
| 28
| UART4_TXD
| ([[#UARTs|UART3 TXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART3_TXD]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 29
| 29
| UART4_RXD
| ([[#UARTs|UART3 RXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART3_RXD]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 0
| 0
| 30
| 30
| UART5_TXD
| ([[#UARTs|UART4 TXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#TS-SOCKET|CN2_090]]
| [[#TS-SOCKET|CN2_090]]
|-
|-
| 0
| 0
| 31
| 31
| UART5_RXD
| ([[#UARTs|UART4 RXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#TS-SOCKET|CN2_092]]
| [[#TS-SOCKET|CN2_092]]
|-
|-
| 2
| 2
| 0
| 0
| LCD_PIX_CLK
| (GPIO) / [[#LCD Interface|LCD CLK]]
| (GPIO) / [[#LCD Interface|LCD CLK]]
| [[#TS-SOCKET|CN1_049]]
| [[#TS-SOCKET|CN1_049]]
Line 174: Line 143:
| 2
| 2
| 1
| 1
| LCD_DE
| (GPIO) / [[#LCD Interface|LCD DE]]
| (GPIO) / [[#LCD Interface|LCD DE]]
| [[#TS-SOCKET|CN1_055]]
| [[#TS-SOCKET|CN1_055]]
Line 180: Line 148:
| 2
| 2
| 2
| 2
| LCD_HSYNC
| (GPIO) / [[#LCD Interface|LCD HSYNC]]
| (GPIO) / [[#LCD Interface|LCD HSYNC]]
| [[#TS-SOCKET|CN1_051]]
| [[#TS-SOCKET|CN1_051]]
Line 186: Line 153:
| 2
| 2
| 3
| 3
| LCD_VSYNC
| (GPIO) / [[#LCD Interface|LCD VSYNC]]
| (GPIO) / [[#LCD Interface|LCD VSYNC]]
| [[#TS-SOCKET|CN1_053]]
| [[#TS-SOCKET|CN1_053]]
Line 192: Line 158:
| 2
| 2
| 7
| 7
| LCD_D02
| (GPIO) / [[#LCD Interface|LCD D02]]
| (GPIO) / [[#LCD Interface|LCD D02]]
| [[#TS-SOCKET|CN1_028]]
| [[#TS-SOCKET|CN1_028]]
Line 198: Line 163:
| 2
| 2
| 8
| 8
| LCD_D03
| (GPIO) / [[#LCD Interface|LCD D03]]
| (GPIO) / [[#LCD Interface|LCD D03]]
| [[#TS-SOCKET|CN1_030]]
| [[#TS-SOCKET|CN1_030]]
Line 204: Line 168:
| 2
| 2
| 9
| 9
| LCD_D04
| (GPIO) / [[#LCD Interface|LCD D04]]
| (GPIO) / [[#LCD Interface|LCD D04]]
| [[#TS-SOCKET|CN1_032]]
| [[#TS-SOCKET|CN1_032]]
Line 210: Line 173:
| 2
| 2
| 10
| 10
| LCD_D05
| (GPIO) / [[#LCD Interface|LCD D05]]
| (GPIO) / [[#LCD Interface|LCD D05]]
| [[#TS-SOCKET|CN1_034]]
| [[#TS-SOCKET|CN1_034]]
Line 216: Line 178:
| 2
| 2
| 11
| 11
| LCD_D06
| (GPIO) / [[#LCD Interface|LCD D06]]
| (GPIO) / [[#LCD Interface|LCD D06]]
| [[#TS-SOCKET|CN1_038]]
| [[#TS-SOCKET|CN1_038]]
Line 222: Line 183:
| 2
| 2
| 12
| 12
| LCD_D07
| (GPIO) / [[#LCD Interface|LCD D07]]
| (GPIO) / [[#LCD Interface|LCD D07]]
| [[#TS-SOCKET|CN1_040]]
| [[#TS-SOCKET|CN1_040]]
Line 228: Line 188:
| 2
| 2
| 13
| 13
| CAN_1_TXD
| ([[#CAN|CAN0 TX]]) / GPIO
| ([[#CAN|CAN0 TX]]) / GPIO
| [[#TS-SOCKET|CN2_097]]
| [[#TS-SOCKET|CN2_097]]
Line 234: Line 193:
| 2
| 2
| 14
| 14
| CAN_1_RXD
| ([[#CAN|CAN0 RX]]) / GPIO
| ([[#CAN|CAN0 RX]]) / GPIO
| [[#TS-SOCKET|CN2_099]]
| [[#TS-SOCKET|CN2_099]]
Line 240: Line 198:
| 2
| 2
| 15
| 15
| LCD_D10
| (GPIO) / [[#LCD Interface|LCD D10]]
| (GPIO) / [[#LCD Interface|LCD D10]]
| [[#TS-SOCKET|CN1_023]]
| [[#TS-SOCKET|CN1_023]]
Line 246: Line 203:
| 2
| 2
| 16
| 16
| LCD_D11
| (GPIO) / [[#LCD Interface|LCD D11]]
| (GPIO) / [[#LCD Interface|LCD D11]]
| [[#TS-SOCKET|CN1_025]]
| [[#TS-SOCKET|CN1_025]]
Line 252: Line 208:
| 2
| 2
| 17
| 17
| LCD_D12
| (GPIO) / [[#LCD Interface|LCD D12]]
| (GPIO) / [[#LCD Interface|LCD D12]]
| [[#TS-SOCKET|CN1_027]]
| [[#TS-SOCKET|CN1_027]]
Line 258: Line 213:
| 2
| 2
| 18
| 18
| LCD_D13
| (GPIO) / [[#LCD Interface|LCD D13]]
| (GPIO) / [[#LCD Interface|LCD D13]]
| [[#TS-SOCKET|CN1_031]]
| [[#TS-SOCKET|CN1_031]]
Line 264: Line 218:
| 2
| 2
| 19
| 19
| LCD_D14
| (GPIO) / [[#LCD Interface|LCD D14]]
| (GPIO) / [[#LCD Interface|LCD D14]]
| [[#TS-SOCKET|CN1_033]]
| [[#TS-SOCKET|CN1_033]]
Line 270: Line 223:
| 2
| 2
| 20
| 20
| LCD_D15
| (GPIO) / [[#LCD Interface|LCD D15]]
| (GPIO) / [[#LCD Interface|LCD D15]]
| [[#TS-SOCKET|CN1_035]]
| [[#TS-SOCKET|CN1_035]]
Line 276: Line 228:
| 2
| 2
| 21
| 21
| UART7_TXD
| ([[#UARTs|UART6 TXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART6_TXD]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 2
| 2
| 22
| 22
| UART7_RXD
| ([[#UARTs|UART6 RXD]]) / GPIO
| ([[#UARTs|UART]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART6_RXD]]
| [[#Crossbar|FPGA Crossbar]]
|-
|-
| 2
| 2
| 23
| 23
| LCD_D18
| ([[#PWM|PWM4]]) / GPIO / [[#LCD Interface|LCD D18]]
| (GPIO) / [[#LCD Interface|LCD D18]]
| [[#TS-SOCKET|CN1_041]]
| [[#TS-SOCKET|CN1_041]]
|-
|-
| 2
| 2
| 24
| 24
| LCD_D19
| ([[#PWM|PWM5]]) / GPIO / [[#LCD Interface|LCD D19]]
| (GPIO) / [[#LCD Interface|LCD D19]]
| [[#TS-SOCKET|CN1_043]]
| [[#TS-SOCKET|CN1_043]]
|-
|-
| 2
| 2
| 25
| 25
| LCD_D20
| (GPIO) / [[#LCD Interface|LCD D20]]
| (GPIO) / [[#LCD Interface|LCD D20]]
| [[#TS-SOCKET|CN1_045]]
| [[#TS-SOCKET|CN1_045]]
Line 306: Line 253:
| 2
| 2
| 26
| 26
| LCD_D21
| (GPIO) / [[#LCD Interface|LCD D21]]
| (GPIO) / [[#LCD Interface|LCD D21]]
| [[#TS-SOCKET|CN1_042]]
| [[#TS-SOCKET|CN1_042]]
Line 312: Line 258:
| 2
| 2
| 27
| 27
| LCD_D22
| (GPIO) / [[#LCD Interface|LCD D22]]
| (GPIO) / [[#LCD Interface|LCD D22]]
| [[#TS-SOCKET|CN1_044]]
| [[#TS-SOCKET|CN1_044]]
Line 318: Line 263:
| 2
| 2
| 28
| 28
| LCD_D23
| (GPIO) / [[#LCD Interface|LCD D23]]
| (GPIO) / [[#LCD Interface|LCD D23]]
| [[#TS-SOCKET|CN1_046]]
| [[#TS-SOCKET|CN1_046]]
Line 324: Line 268:
| 3
| 3
| 10
| 10
| SPI_3_OFF_BD_CS#
| ([[#SPI|SPI2 Offboard CS#]]) / GPIO
| ([[#SPI|SPI]]) / GPIO
| [[#TS-SOCKET|CN2_065]] / [[#HD1_Pin_Header|HD1_13]]
| [[#TS-SOCKET|CN2_065]] / [[#HD1_Pin_Header|HD1_13]]
|-
|-
| 3
| 3
| 11
| 11
| FPGA_RESET#
| (GPIO)
| (GPIO)
| [[#FPGA|FPGA]]
| [[#FPGA|FPGA_RESET#]]
|-
|-
| 3
| 3
| 12
| 12
| SPI_3_FPGA_CS#
| ([[#SPI|SPI2 FPGA CS#]]) / GPIO
| ([[#SPI|SPI]]) / GPIO
| [[#FPGA|FPGA]]
| [[#FPGA|FPGA]]
|-
|-
| 3
| 3
| 13
| 13
| SPI_3_CLK
| ([[#SPI|SPI2 CLK]]) / GPIO
| ([[#SPI|SPI]]) / GPIO
| [[#TS-SOCKET|CN2_071]] / [[#HD1_Pin_Header|HD1_15]] / [[#FPGA|FPGA]]
| [[#TS-SOCKET|CN2_071]] / [[#HD1_Pin_Header|HD1_15]] / [[#FPGA|FPGA]]
|-
|-
| 3
| 3
| 14
| 14
| SPI_3_MOSI
| ([[#SPI|SPI2 MOSI]]) / GPIO
| ([[#SPI|SPI]]) / GPIO
| [[#TS-SOCKET|CN2_067]] / [[#HD1_Pin_Header|HD1_11]] / [[#FPGA|FPGA]]
| [[#TS-SOCKET|CN2_067]] / [[#HD1_Pin_Header|HD1_11]] / [[#FPGA|FPGA]]
|-
|-
| 3
| 3
| 15
| 15
| SPI_3_MISO
| ([[#SPI|SPI2 MISO]]) / GPIO
| ([[#SPI|SPI]]) / GPIO
| [[#TS-SOCKET|CN2_069]] / [[#HD1_Pin_Header|HD1_9]] / [[#FPGA|FPGA]]
| [[#TS-SOCKET|CN2_069]] / [[#HD1_Pin_Header|HD1_9]] / [[#FPGA|FPGA]]
|-
|-
| 3
| 3
| 16
| 16
| SPARE_3
| (GPIO)
| (GPIO)
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar SPARE_3]]
|-
|-
| 3
| 3
| 17
| 17
| CAM_MCLK
| (GPIO) / Camera MCLK
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_034]]
| [[#TS-SOCKET|CN2_034]]
|-
|-
| 3
| 3
| 18
| 18
| CAM_PIX_CLK
| (GPIO) / Camera PIXCLK
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_032]]
| [[#TS-SOCKET|CN2_032]]
|-
|-
| 3
| 3
| 19
| 19
| CAM_VSYNC
| (GPIO) / Camera VSYNC
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_072]]
| [[#TS-SOCKET|CN2_072]]
|-
|-
| 3
| 3
| 20
| 20
| CAM_HSYNC
| (GPIO) / Camera HSYNC
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_070]]
| [[#TS-SOCKET|CN2_070]]
|-
|-
| 3
| 3
| 21
| 21
| CAM_D_0
| (GPIO) / Camera D0
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_052]]
| [[#TS-SOCKET|CN2_052]]
|-
|-
| 3
| 3
| 22
| 22
| CAM_D_1
| (GPIO) / Camera D1
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_056]]
| [[#TS-SOCKET|CN2_056]]
|-
|-
| 3
| 3
| 23
| 23
| CAM_D_2
| (GPIO) / Camera D2
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_058]]
| [[#TS-SOCKET|CN2_058]]
|-
|-
| 3
| 3
| 24
| 24
| CAM_D_3
| (GPIO) / Camera D3
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_060]]
| [[#TS-SOCKET|CN2_060]]
|-
|-
| 3
| 3
| 25
| 25
| CAM_D_4
| (GPIO) / Camera D4
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_062]]
| [[#TS-SOCKET|CN2_062]]
|-
|-
| 3
| 3
| 26
| 26
| CAM_D_5
| (GPIO) / Camera D5
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_064]]
| [[#TS-SOCKET|CN2_064]]
|-
|-
| 3
| 3
| 27
| 27
| CAM_D_6
| (GPIO) / Camera D6
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_066]]
| [[#TS-SOCKET|CN2_066]]
|-
|-
| 3
| 3
| 28
| 28
| CAM_D_7
| (GPIO) / Camera D7
| (GPIO) / Camera Interface
| [[#TS-SOCKET|CN2_068]]
| [[#TS-SOCKET|CN2_068]]
|-
|-
| 4
| 4
| 0
| 0
| POWER_FAIL
| POWER_FAIL<ref>Asserted when external power input falls below valid input range.</ref>
| Power Notification <ref>This will assert high when external power is disconnected.</ref>
| N/A
| N/A
|-
|-
| 4
| 4
| 1
| 1
| FPGA_IRQ
| [[#ZPU|ZPU IRQ]]
| [[#ZPU|ZPU IRQ]]
| [[#FPGA|FPGA]]
| [[#FPGA|FPGA]]
Line 450: Line 373:
| 4
| 4
| 8
| 8
| SPARE_4
| ([[#Wi-Fi|Wi-Fi IRQ]]) / GPIO
| ([[#Wi-Fi|Wi-Fi IRQ]]) / GPIO
| [[#Crossbar|FPGA Crossbar]]
| [[#Crossbar|FPGA Crossbar SPARE_4]]
|}
|}


<References />
<references/>

Latest revision as of 17:12, 26 July 2019

Chip Pin Functions Location
0 0 (USB1 OTG ID) / GPIO CN2_074
0 1 (GPIO) / ADC input CN2_012
0 8 (PWM0) / ADC input / GPIO CN1_057
0 9 (PWM1) / ADC input / GPIO CN2_091
0 10 (Ethernet PHY power en.) / GPIO CN2_046
0 11 (I2S Master Clock) / GPIO CN2_054
0 12 (I2S TX Sync) / GPIO CN2_038
0 13 (I2S TX Bit Clock) / GPIO CN2_036
0 14 (I2S RX Data) / GPIO CN2_042
0 15 (I2S TX Data) / GPIO CN2_040
0 16 (Console UART TXD) / GPIO CN2_093 / Microcontroller
0 17 (Console UART RXD) / GPIO CN2_095 / Microcontroller
0 18 (GPIO) FPGA Crossbar SPARE_1
0 19 (GPIO) FPGA Crossbar SPARE_2
0 20 (UART1 TXD) / GPIO CN2_082
0 21 (UART1 RXD) / GPIO CN2_084
0 22 (CAN1 TX) / GPIO CN1_071
0 23 (CAN1 RX) / GPIO CN1_069
0 24 (UART2 TXD) / GPIO FPGA Crossbar UART2_TXD
0 25 (UART2 RXD) / GPIO FPGA Crossbar UART2_RXD
0 26 (UART2 CTS) / GPIO FPGA Crossbar UART2_CTS
0 27 (UART2 RTS) / GPIO FPGA Crossbar UART2_RTS
0 28 (UART3 TXD) / GPIO FPGA Crossbar UART3_TXD
0 29 (UART3 RXD) / GPIO FPGA Crossbar UART3_RXD
0 30 (UART4 TXD) / GPIO CN2_090
0 31 (UART4 RXD) / GPIO CN2_092
2 0 (GPIO) / LCD CLK CN1_049
2 1 (GPIO) / LCD DE CN1_055
2 2 (GPIO) / LCD HSYNC CN1_051
2 3 (GPIO) / LCD VSYNC CN1_053
2 7 (GPIO) / LCD D02 CN1_028
2 8 (GPIO) / LCD D03 CN1_030
2 9 (GPIO) / LCD D04 CN1_032
2 10 (GPIO) / LCD D05 CN1_034
2 11 (GPIO) / LCD D06 CN1_038
2 12 (GPIO) / LCD D07 CN1_040
2 13 (CAN0 TX) / GPIO CN2_097
2 14 (CAN0 RX) / GPIO CN2_099
2 15 (GPIO) / LCD D10 CN1_023
2 16 (GPIO) / LCD D11 CN1_025
2 17 (GPIO) / LCD D12 CN1_027
2 18 (GPIO) / LCD D13 CN1_031
2 19 (GPIO) / LCD D14 CN1_033
2 20 (GPIO) / LCD D15 CN1_035
2 21 (UART6 TXD) / GPIO FPGA Crossbar UART6_TXD
2 22 (UART6 RXD) / GPIO FPGA Crossbar UART6_RXD
2 23 (PWM4) / GPIO / LCD D18 CN1_041
2 24 (PWM5) / GPIO / LCD D19 CN1_043
2 25 (GPIO) / LCD D20 CN1_045
2 26 (GPIO) / LCD D21 CN1_042
2 27 (GPIO) / LCD D22 CN1_044
2 28 (GPIO) / LCD D23 CN1_046
3 10 (SPI2 Offboard CS#) / GPIO CN2_065 / HD1_13
3 11 (GPIO) FPGA_RESET#
3 12 (SPI2 FPGA CS#) / GPIO FPGA
3 13 (SPI2 CLK) / GPIO CN2_071 / HD1_15 / FPGA
3 14 (SPI2 MOSI) / GPIO CN2_067 / HD1_11 / FPGA
3 15 (SPI2 MISO) / GPIO CN2_069 / HD1_9 / FPGA
3 16 (GPIO) FPGA Crossbar SPARE_3
3 17 (GPIO) / Camera MCLK CN2_034
3 18 (GPIO) / Camera PIXCLK CN2_032
3 19 (GPIO) / Camera VSYNC CN2_072
3 20 (GPIO) / Camera HSYNC CN2_070
3 21 (GPIO) / Camera D0 CN2_052
3 22 (GPIO) / Camera D1 CN2_056
3 23 (GPIO) / Camera D2 CN2_058
3 24 (GPIO) / Camera D3 CN2_060
3 25 (GPIO) / Camera D4 CN2_062
3 26 (GPIO) / Camera D5 CN2_064
3 27 (GPIO) / Camera D6 CN2_066
3 28 (GPIO) / Camera D7 CN2_068
4 0 POWER_FAIL[1] N/A
4 1 ZPU IRQ FPGA
4 8 (Wi-Fi IRQ) / GPIO FPGA Crossbar SPARE_4
  1. ↑ Asserted when external power input falls below valid input range.
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