TS-4100 CPU DIO Table: Difference between revisions

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The GPIO numbers in the table below are relevant to how the Linux references these numbers.  The CPU documentation refers to bank and IO while Linux flattens this out to one number space. 
{| class="wikitable sortable"
{| class="wikitable sortable"
|-
|-
! Schematic Name
! Chip
! CPU PAD <ref> The pad name does not often correspond with the functionality of the IO we use, but can be used to reference the pad in the CPU manual.</ref>
! Pin
! GPIO Number
! Functions
! Common Functions <ref>This does not contain all of the functions possible for a pin, but the common functions as they are used on our off the shelf basebords.  Consult the i.MX6 CPU Reference manual for a complete list.</ref>
! Location
! Location
|-
|-
| CONSOLE_RXD
| 0
| UART1_RX_DATA
| 0
| 17
| ([[#USB|USB1 OTG ID]]) / GPIO
| Console uart
| [[#TS-SOCKET|CN2_074]]
| CN2_095 / Silabs
|-
| 0
| 1
| (GPIO) / [[#ADC|ADC input]]
| [[#TS-SOCKET|CN2_012]]
|-
| 0
| 8
| ([[#PWM|PWM0]]) / [[#ADC|ADC input]] / GPIO
| [[#TS-SOCKET|CN1_057]]
|-
| 0
| 9
| ([[#PWM|PWM1]]) / [[#ADC|ADC input]] / GPIO
| [[#TS-SOCKET|CN2_091]]
|-
| 0
| 10
| ([[#Ethernet|Ethernet PHY power en.]]) / GPIO
| [[#TS-SOCKET|CN2_046]]
|-
|0
| 11
| ([[#I2S_Audio|I2S Master Clock]]) / GPIO
| [[#TS-SOCKET|CN2_054]]
|-
| 0
| 12
| ([[#I2S_Audio|I2S TX Sync]]) / GPIO
| [[#TS-SOCKET|CN2_038]]
|-
| 0
| 13
| ([[#I2S_Audio|I2S TX Bit Clock]]) / GPIO
| [[#TS-SOCKET|CN2_036]]
|-
| 0
| 14
| ([[#I2S_Audio|I2S RX Data]]) / GPIO
| [[#TS-SOCKET|CN2_042]]
|-
| 0
| 15
| ([[#I2S_Audio|I2S TX Data]]) / GPIO
| [[#TS-SOCKET|CN2_040]]
|-
|-
| CONSOLE_TXD
| 0
| UART1_TX_DATA
| 16
| 16
| Console uart
| ([[#UARTs|Console UART TXD]]) / GPIO
| CN2_093 / Silabs
| [[#TS-SOCKET|CN2_093]] / [[#Supervisory Microcontroller|Microcontroller]]
|-
| 0
| 17
| ([[#UARTs|Console UART RXD]]) / GPIO
| [[#TS-SOCKET|CN2_095]] / [[#Supervisory Microcontroller|Microcontroller]]
|-
|-
| SPARE_1
| 0
| UART1_CTS_B
| 18
| 18
| GPIO
| (GPIO)
| [[#FPGA|FPGA Crossbar]] (Default NC)
| [[#Crossbar|FPGA Crossbar SPARE_1]]
|-
|-
| SPARE_2
| 0
| UART1_RTS_B
| 19
| 19
| GPIO
| (GPIO)
| [[#FPGA|FPGA Crossbar]] (Default NC)
| [[#Crossbar|FPGA Crossbar SPARE_2]]
|-
| 0
| 20
| ([[#UARTs|UART1 TXD]]) / GPIO
| [[#TS-SOCKET|CN2_082]]
|-
|-
| UART2_RXD
| 0
| UART2_RX_DATA
| 21
| 21
| [[#COM_Ports]]
| ([[#UARTs|UART1 RXD]]) / GPIO
| CN2_084
| [[#TS-SOCKET|CN2_084]]
|-
| UART2_TXD
| UART2_TX_DATA
| 20
| [[#COM_Ports]]
| CN2_082
|-
|-
| CAN_2_TXD
| 0
| UART2_CTS_B
| 22
| 22
| [[#CAN]]
| ([[#CAN|CAN1 TX]]) / GPIO
| CN1_071
| [[#TS-SOCKET|CN1_071]]
|-
|-
| CAN_2_RXD
| 0
| UART2_RTS_B
| 23
| 23
| [[#CAN]]
| ([[#CAN|CAN1 RX]]) / GPIO
| CN1_069
| [[#TS-SOCKET|CN1_069]]
|-
| 0
| 24
| ([[#UARTs|UART2 TXD]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART2_TXD]]
|-
|-
| UART3_RXD
| 0
| UART3_RX_DATA
| 25
| 25
| [[#COM_Ports]]
| ([[#UARTs|UART2 RXD]]) / GPIO
| [[#FPGA|FPGA Crossbar]] (Default Bluetooth RX)
| [[#Crossbar|FPGA Crossbar UART2_RXD]]
|-
| UART3_TXD
| UART3_TX_DATA
| 24
| [[#COM_Ports]]
| [[#FPGA|FPGA Crossbar]] (Default Bluetooth TX)
|-
|-
| UART3_CTS#
| 0
| UART3_CTS_B
| 26
| 26
| [[#COM_Ports]]
| ([[#UARTs|UART2 CTS]]) / GPIO
| [[#FPGA|FPGA Crossbar]] (Default Bluetooth CTS)
| [[#Crossbar|FPGA Crossbar UART2_CTS]]
|-
|-
| UART3_RTS#
| 0
| UART3_RTS_B
| 27
| 27
| [[#COM_Ports]]
| ([[#UARTs|UART2 RTS]]) / GPIO
| [[#FPGA|FPGA Crossbar]] (Default Bluetooth RTS)
| [[#Crossbar|FPGA Crossbar UART2_RTS]]  
|-
| 0
| 28
| ([[#UARTs|UART3 TXD]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART3_TXD]]
|-
|-
| UART4_RXD
| 0
| UART4_RX_DATA
| 29
| 29
| [[#COM_Ports]]
| ([[#UARTs|UART3 RXD]]) / GPIO
| [[#FPGA|FPGA Crossbar]] (Default CN2_080)
| [[#Crossbar|FPGA Crossbar UART3_RXD]]
|-
|-
| UART4_TXD
| 0
| UART4_TX_DATA
| 30
| 28
| ([[#UARTs|UART4 TXD]]) / GPIO
| [[#COM_Ports]]
| [[#TS-SOCKET|CN2_090]]
| [[#FPGA|FPGA Crossbar]] (Default CN2_078)
|-
|-
| UART5_RXD
| 0
| UART5_RX_DATA
| 31
| 31
| [[#COM_Ports]]
| ([[#UARTs|UART4 RXD]]) / GPIO
| CN2_092
| [[#TS-SOCKET|CN2_092]]
|-
|-
| UART5_TXD
| 2
| UART5_TX_DATA
| 0
| 30
| (GPIO) / [[#LCD Interface|LCD CLK]]
| [[#COM_Ports]]
| [[#TS-SOCKET|CN1_049]]
| CN2_090
|-
| 2
| 1
| (GPIO) / [[#LCD Interface|LCD DE]]
| [[#TS-SOCKET|CN1_055]]
|-
| 2
| 2
| (GPIO) / [[#LCD Interface|LCD HSYNC]]
| [[#TS-SOCKET|CN1_051]]
|-
| 2
| 3
| (GPIO) / [[#LCD Interface|LCD VSYNC]]
| [[#TS-SOCKET|CN1_053]]
|-
| 2
| 7
| (GPIO) / [[#LCD Interface|LCD D02]]
| [[#TS-SOCKET|CN1_028]]
|-
| 2
| 8
| (GPIO) / [[#LCD Interface|LCD D03]]
| [[#TS-SOCKET|CN1_030]]
|-
| 2
| 9
| (GPIO) / [[#LCD Interface|LCD D04]]
| [[#TS-SOCKET|CN1_032]]
|-
| 2
| 10
| (GPIO) / [[#LCD Interface|LCD D05]]
| [[#TS-SOCKET|CN1_034]]
|-
| 2
| 11
| (GPIO) / [[#LCD Interface|LCD D06]]
| [[#TS-SOCKET|CN1_038]]
|-
| 2
| 12
| (GPIO) / [[#LCD Interface|LCD D07]]
| [[#TS-SOCKET|CN1_040]]
|-
| 2
| 13
| ([[#CAN|CAN0 TX]]) / GPIO
| [[#TS-SOCKET|CN2_097]]
|-
|-
| AUD_RXD
| 2
| JTAG_TCK
| 14
| 14
| [[#I2S]] / [[#JTAG]]
| ([[#CAN|CAN0 RX]]) / GPIO
| CN2_042
| [[#TS-SOCKET|CN2_099]]
|-
| 2
| 15
| (GPIO) / [[#LCD Interface|LCD D10]]
| [[#TS-SOCKET|CN1_023]]
|-
| 2
| 16
| (GPIO) / [[#LCD Interface|LCD D11]]
| [[#TS-SOCKET|CN1_025]]
|-
| 2
| 17
| (GPIO) / [[#LCD Interface|LCD D12]]
| [[#TS-SOCKET|CN1_027]]
|-
| 2
| 18
| (GPIO) / [[#LCD Interface|LCD D13]]
| [[#TS-SOCKET|CN1_031]]
|-
| 2
| 19
| (GPIO) / [[#LCD Interface|LCD D14]]
| [[#TS-SOCKET|CN1_033]]
|-
| 2
| 20
| (GPIO) / [[#LCD Interface|LCD D15]]
| [[#TS-SOCKET|CN1_035]]
|-
| 2
| 21
| ([[#UARTs|UART6 TXD]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART6_TXD]]
|-
| 2
| 22
| ([[#UARTs|UART6 RXD]]) / GPIO
| [[#Crossbar|FPGA Crossbar UART6_RXD]]
|-
| 2
| 23
| ([[#PWM|PWM4]]) / GPIO / [[#LCD Interface|LCD D18]]
| [[#TS-SOCKET|CN1_041]]
|-
| 2
| 24
| ([[#PWM|PWM5]]) / GPIO / [[#LCD Interface|LCD D19]]
| [[#TS-SOCKET|CN1_043]]
|-
| 2
| 25
| (GPIO) / [[#LCD Interface|LCD D20]]
| [[#TS-SOCKET|CN1_045]]
|-
| 2
| 26
| (GPIO) / [[#LCD Interface|LCD D21]]
| [[#TS-SOCKET|CN1_042]]
|-
| 2
| 27
| (GPIO) / [[#LCD Interface|LCD D22]]
| [[#TS-SOCKET|CN1_044]]
|-
| 2
| 28
| (GPIO) / [[#LCD Interface|LCD D23]]
| [[#TS-SOCKET|CN1_046]]
|-
| 3
| 10
| ([[#SPI|SPI2 Offboard CS#]]) / GPIO
| [[#TS-SOCKET|CN2_065]] / [[#HD1_Pin_Header|HD1_13]]
|-
|-
| AUD_CLK
| 3
| JTAG_TDI
| 11
| 13
| (GPIO)
| [[#I2S]] / [[#JTAG]]
| [[#FPGA|FPGA_RESET#]]
| CN2_036
|-
|-
| AUD_FRM
| 3
| JTAG_TDO
| 12
| 12
| [[#I2S]] / [[#JTAG]]
| ([[#SPI|SPI2 FPGA CS#]]) / GPIO
| CN2_038
| [[#FPGA|FPGA]]
|-
|-
| AUD_MCLK
| 3
| JTAG_TMS
| 13
| 11
| ([[#SPI|SPI2 CLK]]) / GPIO
| [[#I2S]] / [[#JTAG]]
| [[#TS-SOCKET|CN2_071]] / [[#HD1_Pin_Header|HD1_15]] / [[#FPGA|FPGA]]
| CN2_54
|-
| 3
| 14
| ([[#SPI|SPI2 MOSI]]) / GPIO
| [[#TS-SOCKET|CN2_067]] / [[#HD1_Pin_Header|HD1_11]] / [[#FPGA|FPGA]]
|-
|-
| AUD_TXD
| 3
| JTAG_TRST_B
| 15
| 15
| [[#I2S]] / [[#JTAG]]
| ([[#SPI|SPI2 MISO]]) / GPIO
| CN2_040
| [[#TS-SOCKET|CN2_069]] / [[#HD1_Pin_Header|HD1_9]] / [[#FPGA|FPGA]]
|-
|-
| EN_ETH_PHY_PWR
| 3
| JTAG_MOD
| 16
| 10
| (GPIO)
| Eth PHY enable / [[#JTAG]]
| [[#Crossbar|FPGA Crossbar SPARE_3]]
| CN2_046
|-
| 3
| 17
| (GPIO) / Camera MCLK
| [[#TS-SOCKET|CN2_034]]
|-
| 3
| 18
| (GPIO) / Camera PIXCLK
| [[#TS-SOCKET|CN2_032]]
|-
| 3
| 19
| (GPIO) / Camera VSYNC
| [[#TS-SOCKET|CN2_072]]
|-
| 3
| 20
| (GPIO) / Camera HSYNC
| [[#TS-SOCKET|CN2_070]]
|-
|-
| CAM_D_0
| 3
| CSI_DATA00
| 21
| 117
| (GPIO) / Camera D0
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_052]]
| CN2_052
|-
|-
| CAM_D_1
| 3
| CSI_DATA01
| 22
| 118
| (GPIO) / Camera D1
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_056]]
| CN2_056
|-
|-
| CAM_D_2
| 3
| CSI_DATA02
| 23
| 119
| (GPIO) / Camera D2
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_058]]
| CN2_058
|-
|-
| CAM_D_3
| 3
| CSI_DATA03
| 24
| 120
| (GPIO) / Camera D3
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_060]]
| CN2_060
|-
|-
| CAM_D_4
| 3
| CSI_DATA04
| 25
| 121
| (GPIO) / Camera D4
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_062]]
| CN2_062
|-
|-
| CAM_D_5
| 3
| CSI_DATA05
| 26
| 122
| (GPIO) / Camera D5
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_064]]
| CN2_064
|-
|-
| CAM_D_6
| 3
| CSI_DATA06
| 27
| 123
| (GPIO) / Camera D6
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_066]]
| CN2_066
|-
|-
| CAM_D_7
| 3
| CSI_DATA07
| 28
| 124
| (GPIO) / Camera D7
| [[#Camera Interface]] / GPIO
| [[#TS-SOCKET|CN2_068]]
| CN2_068
|-
|-
| CAM_HSYNC
| 4
| CSI_HSYNC
| 0
| 116
| POWER_FAIL<ref>Asserted when external power input falls below valid input range.</ref>
| [[#Camera Interface]] / GPIO
| N/A
| CN2_070
|-
|-
| CAM_VSYNC
| 4
| CSI_VSYNC
| 1
| 115
| [[#ZPU|ZPU IRQ]]
| [[#Camera Interface]] / GPIO
| [[#FPGA|FPGA]]
| CN2_072
|-
|-
|  
| 4
| 8
| ([[#Wi-Fi|Wi-Fi IRQ]]) / GPIO
| [[#Crossbar|FPGA Crossbar SPARE_4]]
|}
|}


<References />
<references/>

Latest revision as of 17:12, 26 July 2019

Chip Pin Functions Location
0 0 (USB1 OTG ID) / GPIO CN2_074
0 1 (GPIO) / ADC input CN2_012
0 8 (PWM0) / ADC input / GPIO CN1_057
0 9 (PWM1) / ADC input / GPIO CN2_091
0 10 (Ethernet PHY power en.) / GPIO CN2_046
0 11 (I2S Master Clock) / GPIO CN2_054
0 12 (I2S TX Sync) / GPIO CN2_038
0 13 (I2S TX Bit Clock) / GPIO CN2_036
0 14 (I2S RX Data) / GPIO CN2_042
0 15 (I2S TX Data) / GPIO CN2_040
0 16 (Console UART TXD) / GPIO CN2_093 / Microcontroller
0 17 (Console UART RXD) / GPIO CN2_095 / Microcontroller
0 18 (GPIO) FPGA Crossbar SPARE_1
0 19 (GPIO) FPGA Crossbar SPARE_2
0 20 (UART1 TXD) / GPIO CN2_082
0 21 (UART1 RXD) / GPIO CN2_084
0 22 (CAN1 TX) / GPIO CN1_071
0 23 (CAN1 RX) / GPIO CN1_069
0 24 (UART2 TXD) / GPIO FPGA Crossbar UART2_TXD
0 25 (UART2 RXD) / GPIO FPGA Crossbar UART2_RXD
0 26 (UART2 CTS) / GPIO FPGA Crossbar UART2_CTS
0 27 (UART2 RTS) / GPIO FPGA Crossbar UART2_RTS
0 28 (UART3 TXD) / GPIO FPGA Crossbar UART3_TXD
0 29 (UART3 RXD) / GPIO FPGA Crossbar UART3_RXD
0 30 (UART4 TXD) / GPIO CN2_090
0 31 (UART4 RXD) / GPIO CN2_092
2 0 (GPIO) / LCD CLK CN1_049
2 1 (GPIO) / LCD DE CN1_055
2 2 (GPIO) / LCD HSYNC CN1_051
2 3 (GPIO) / LCD VSYNC CN1_053
2 7 (GPIO) / LCD D02 CN1_028
2 8 (GPIO) / LCD D03 CN1_030
2 9 (GPIO) / LCD D04 CN1_032
2 10 (GPIO) / LCD D05 CN1_034
2 11 (GPIO) / LCD D06 CN1_038
2 12 (GPIO) / LCD D07 CN1_040
2 13 (CAN0 TX) / GPIO CN2_097
2 14 (CAN0 RX) / GPIO CN2_099
2 15 (GPIO) / LCD D10 CN1_023
2 16 (GPIO) / LCD D11 CN1_025
2 17 (GPIO) / LCD D12 CN1_027
2 18 (GPIO) / LCD D13 CN1_031
2 19 (GPIO) / LCD D14 CN1_033
2 20 (GPIO) / LCD D15 CN1_035
2 21 (UART6 TXD) / GPIO FPGA Crossbar UART6_TXD
2 22 (UART6 RXD) / GPIO FPGA Crossbar UART6_RXD
2 23 (PWM4) / GPIO / LCD D18 CN1_041
2 24 (PWM5) / GPIO / LCD D19 CN1_043
2 25 (GPIO) / LCD D20 CN1_045
2 26 (GPIO) / LCD D21 CN1_042
2 27 (GPIO) / LCD D22 CN1_044
2 28 (GPIO) / LCD D23 CN1_046
3 10 (SPI2 Offboard CS#) / GPIO CN2_065 / HD1_13
3 11 (GPIO) FPGA_RESET#
3 12 (SPI2 FPGA CS#) / GPIO FPGA
3 13 (SPI2 CLK) / GPIO CN2_071 / HD1_15 / FPGA
3 14 (SPI2 MOSI) / GPIO CN2_067 / HD1_11 / FPGA
3 15 (SPI2 MISO) / GPIO CN2_069 / HD1_9 / FPGA
3 16 (GPIO) FPGA Crossbar SPARE_3
3 17 (GPIO) / Camera MCLK CN2_034
3 18 (GPIO) / Camera PIXCLK CN2_032
3 19 (GPIO) / Camera VSYNC CN2_072
3 20 (GPIO) / Camera HSYNC CN2_070
3 21 (GPIO) / Camera D0 CN2_052
3 22 (GPIO) / Camera D1 CN2_056
3 23 (GPIO) / Camera D2 CN2_058
3 24 (GPIO) / Camera D3 CN2_060
3 25 (GPIO) / Camera D4 CN2_062
3 26 (GPIO) / Camera D5 CN2_064
3 27 (GPIO) / Camera D6 CN2_066
3 28 (GPIO) / Camera D7 CN2_068
4 0 POWER_FAIL[1] N/A
4 1 ZPU IRQ FPGA
4 8 (Wi-Fi IRQ) / GPIO FPGA Crossbar SPARE_4
  1. ↑ Asserted when external power input falls below valid input range.
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