TS-4100 CPU DIO Table: Difference between revisions
From embeddedTS Manuals
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{| class="wikitable sortable" | {| class="wikitable sortable" | ||
|- | |- | ||
! | ! Chip | ||
! | ! Pin | ||
! | ! Functions | ||
! Location | ! Location | ||
|- | |- | ||
| | | 0 | ||
| | | 0 | ||
| | | ([[#USB|USB1 OTG ID]]) / GPIO | ||
| | | [[#TS-SOCKET|CN2_074]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 1 | ||
| | | (GPIO) / [[#ADC|ADC input]] | ||
| | | [[#TS-SOCKET|CN2_012]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 8 | ||
| | | ([[#PWM|PWM0]]) / [[#ADC|ADC input]] / GPIO | ||
| GPIO | | [[#TS-SOCKET|CN1_057]] | ||
| [[# | |||
|- | |- | ||
| | | 0 | ||
| | | 9 | ||
| | | ([[#PWM|PWM1]]) / [[#ADC|ADC input]] / GPIO | ||
| GPIO | | [[#TS-SOCKET|CN2_091]] | ||
| [[# | |||
|- | |- | ||
| | | 0 | ||
| | | 10 | ||
| | | ([[#Ethernet|Ethernet PHY power en.]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_046]] | ||
|- | |- | ||
| | |0 | ||
| | | 11 | ||
| | | ([[#I2S_Audio|I2S Master Clock]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_054]] | ||
|- | |- | ||
| | | 0 | ||
| | | 12 | ||
| | | ([[#I2S_Audio|I2S TX Sync]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_038]] | ||
|- | |- | ||
| | | 0 | ||
| | | 13 | ||
| | | ([[#I2S_Audio|I2S TX Bit Clock]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_036]] | ||
|- | |- | ||
| | | 0 | ||
| 14 | | 14 | ||
| [[#I2S]] / [[# | | ([[#I2S_Audio|I2S RX Data]]) / GPIO | ||
| [[#TS-SOCKET|CN2_042]] | |||
|- | |- | ||
| | | 0 | ||
| | | 15 | ||
| ([[#I2S_Audio|I2S TX Data]]) / GPIO | |||
| [[#I2S]] / [[# | | [[#TS-SOCKET|CN2_040]] | ||
|- | |- | ||
| | | 0 | ||
| | | 16 | ||
| | | ([[#UARTs|Console UART TXD]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_093]] / [[#Supervisory Microcontroller|Microcontroller]] | ||
|- | |- | ||
| | | 0 | ||
| | | 17 | ||
| | | ([[#UARTs|Console UART RXD]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_095]] / [[#Supervisory Microcontroller|Microcontroller]] | ||
|- | |- | ||
| | | 0 | ||
| | | 18 | ||
| | | (GPIO) | ||
| [[# | | [[#Crossbar|FPGA Crossbar SPARE_1]] | ||
|- | |- | ||
| | | 0 | ||
| | | 19 | ||
| | | (GPIO) | ||
| | | [[#Crossbar|FPGA Crossbar SPARE_2]] | ||
|- | |- | ||
| | | 0 | ||
| | | 20 | ||
| ([[#UARTs|UART1 TXD]]) / GPIO | |||
| [[# | | [[#TS-SOCKET|CN2_082]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 21 | ||
| ([[#UARTs|UART1 RXD]]) / GPIO | |||
| [[# | | [[#TS-SOCKET|CN2_084]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 22 | ||
| ([[#CAN|CAN1 TX]]) / GPIO | |||
| [[# | | [[#TS-SOCKET|CN1_071]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 23 | ||
| ([[#CAN|CAN1 RX]]) / GPIO | |||
| [[# | | [[#TS-SOCKET|CN1_069]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 24 | ||
| ([[#UARTs|UART2 TXD]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar UART2_TXD]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 25 | ||
| ([[#UARTs|UART2 RXD]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar UART2_RXD]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 26 | ||
| ([[#UARTs|UART2 CTS]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar UART2_CTS]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 27 | ||
| ([[#UARTs|UART2 RTS]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar UART2_RTS]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 28 | ||
| ([[#UARTs|UART3 TXD]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar UART3_TXD]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 29 | ||
| ([[#UARTs|UART3 RXD]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar UART3_RXD]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 30 | ||
| ([[#UARTs|UART4 TXD]]) / GPIO | |||
| [[# | | [[#TS-SOCKET|CN2_090]] | ||
| | |||
|- | |- | ||
| | | 0 | ||
| | | 31 | ||
| ([[#UARTs|UART4 RXD]]) / GPIO | |||
| [[# | | [[#TS-SOCKET|CN2_092]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| 0 | | 0 | ||
| [[# | | (GPIO) / [[#LCD Interface|LCD CLK]] | ||
| | | [[#TS-SOCKET|CN1_049]] | ||
|- | |- | ||
| | | 2 | ||
| 1 | | 1 | ||
| [[# | | (GPIO) / [[#LCD Interface|LCD DE]] | ||
| | | [[#TS-SOCKET|CN1_055]] | ||
|- | |- | ||
| 2 | | 2 | ||
| [[# | | 2 | ||
| | | (GPIO) / [[#LCD Interface|LCD HSYNC]] | ||
| [[#TS-SOCKET|CN1_051]] | |||
|- | |- | ||
| | | 2 | ||
| 3 | | 3 | ||
| [[# | | (GPIO) / [[#LCD Interface|LCD VSYNC]] | ||
| | | [[#TS-SOCKET|CN1_053]] | ||
|- | |- | ||
| | | 2 | ||
| 7 | | 7 | ||
| [[# | | (GPIO) / [[#LCD Interface|LCD D02]] | ||
| | | [[#TS-SOCKET|CN1_028]] | ||
|- | |- | ||
| | | 2 | ||
| 8 | | 8 | ||
| [[# | | (GPIO) / [[#LCD Interface|LCD D03]] | ||
| [[#TS-SOCKET|CN1_030]] | |||
|- | |- | ||
| | | 2 | ||
| 9 | | 9 | ||
| [[# | | (GPIO) / [[#LCD Interface|LCD D04]] | ||
| | | [[#TS-SOCKET|CN1_032]] | ||
|- | |- | ||
| | | 2 | ||
| | | 10 | ||
| | | (GPIO) / [[#LCD Interface|LCD D05]] | ||
| | | [[#TS-SOCKET|CN1_034]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 11 | ||
| (GPIO) / [[#LCD Interface|LCD D06]] | |||
| [[# | | [[#TS-SOCKET|CN1_038]] | ||
| [[# | |||
|- | |- | ||
| | | 2 | ||
| | | 12 | ||
| | | (GPIO) / [[#LCD Interface|LCD D07]] | ||
| | | [[#TS-SOCKET|CN1_040]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 13 | ||
| | | ([[#CAN|CAN0 TX]]) / GPIO | ||
| | | [[#TS-SOCKET|CN2_097]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 14 | ||
| | | ([[#CAN|CAN0 RX]]) / GPIO | ||
| | | [[#TS-SOCKET|CN2_099]] | ||
| [[# | |||
|- | |- | ||
| | | 2 | ||
| | | 15 | ||
| | | (GPIO) / [[#LCD Interface|LCD D10]] | ||
| | | [[#TS-SOCKET|CN1_023]] | ||
| [[# | |||
|- | |- | ||
| | | 2 | ||
| | | 16 | ||
| | | (GPIO) / [[#LCD Interface|LCD D11]] | ||
| | | [[#TS-SOCKET|CN1_025]] | ||
| [[# | |||
|- | |- | ||
| | | 2 | ||
| | | 17 | ||
| | | (GPIO) / [[#LCD Interface|LCD D12]] | ||
| | | [[#TS-SOCKET|CN1_027]] | ||
| [[# | |||
|- | |- | ||
| | | 2 | ||
| | | 18 | ||
| | | (GPIO) / [[#LCD Interface|LCD D13]] | ||
| | | [[#TS-SOCKET|CN1_031]] | ||
| [[# | |||
|- | |- | ||
| | | 2 | ||
| | | 19 | ||
| | | (GPIO) / [[#LCD Interface|LCD D14]] | ||
| | | [[#TS-SOCKET|CN1_033]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 20 | ||
| | | (GPIO) / [[#LCD Interface|LCD D15]] | ||
| [[# | | [[#TS-SOCKET|CN1_035]] | ||
|- | |- | ||
| | | 2 | ||
| | | 21 | ||
| ([[#UARTs|UART6 TXD]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar UART6_TXD]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 22 | ||
| ([[#UARTs|UART6 RXD]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar UART6_RXD]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 23 | ||
| | | ([[#PWM|PWM4]]) / GPIO / [[#LCD Interface|LCD D18]] | ||
| [[# | | [[#TS-SOCKET|CN1_041]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 24 | ||
| | | ([[#PWM|PWM5]]) / GPIO / [[#LCD Interface|LCD D19]] | ||
| [[# | | [[#TS-SOCKET|CN1_043]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 25 | ||
| (GPIO) / [[#LCD Interface|LCD D20]] | |||
| [[# | | [[#TS-SOCKET|CN1_045]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 26 | ||
| (GPIO) / [[#LCD Interface|LCD D21]] | |||
| [[# | | [[#TS-SOCKET|CN1_042]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 27 | ||
| (GPIO) / [[#LCD Interface|LCD D22]] | |||
| [[# | | [[#TS-SOCKET|CN1_044]] | ||
| | |||
|- | |- | ||
| | | 2 | ||
| | | 28 | ||
| | | (GPIO) / [[#LCD Interface|LCD D23]] | ||
| [[# | | [[#TS-SOCKET|CN1_046]] | ||
|- | |- | ||
| | | 3 | ||
| | | 10 | ||
| | | ([[#SPI|SPI2 Offboard CS#]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_065]] / [[#HD1_Pin_Header|HD1_13]] | ||
| | |||
|- | |- | ||
| | | 3 | ||
| | | 11 | ||
| | | (GPIO) | ||
| [[# | | [[#FPGA|FPGA_RESET#]] | ||
|- | |- | ||
| | | 3 | ||
| | | 12 | ||
| ([[#SPI|SPI2 FPGA CS#]]) / GPIO | |||
| [[# | | [[#FPGA|FPGA]] | ||
| | |||
|- | |- | ||
| | | 3 | ||
| | | 13 | ||
| | | ([[#SPI|SPI2 CLK]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_071]] / [[#HD1_Pin_Header|HD1_15]] / [[#FPGA|FPGA]] | ||
| | |||
|- | |- | ||
| | | 3 | ||
| | | 14 | ||
| | | ([[#SPI|SPI2 MOSI]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_067]] / [[#HD1_Pin_Header|HD1_11]] / [[#FPGA|FPGA]] | ||
| | |||
|- | |- | ||
| | | 3 | ||
| | | 15 | ||
| | | ([[#SPI|SPI2 MISO]]) / GPIO | ||
| [[# | | [[#TS-SOCKET|CN2_069]] / [[#HD1_Pin_Header|HD1_9]] / [[#FPGA|FPGA]] | ||
| | |||
|- | |- | ||
| | | 3 | ||
| | | 16 | ||
| | | (GPIO) | ||
| [[# | | [[#Crossbar|FPGA Crossbar SPARE_3]] | ||
|- | |- | ||
| | | 3 | ||
| | | 17 | ||
| | | (GPIO) / Camera MCLK | ||
| [[# | | [[#TS-SOCKET|CN2_034]] | ||
| | |||
|- | |- | ||
| | | 3 | ||
| | | 18 | ||
| | | (GPIO) / Camera PIXCLK | ||
| [[# | | [[#TS-SOCKET|CN2_032]] | ||
| | |||
|- | |- | ||
| | | 3 | ||
| | | 19 | ||
| | | (GPIO) / Camera VSYNC | ||
| [[# | | [[#TS-SOCKET|CN2_072]] | ||
|- | |- | ||
| | | 3 | ||
| | | 20 | ||
| | | (GPIO) / Camera HSYNC | ||
| [[# | | [[#TS-SOCKET|CN2_070]] | ||
|- | |- | ||
| | | 3 | ||
| | | 21 | ||
| | | (GPIO) / Camera D0 | ||
| [[# | | [[#TS-SOCKET|CN2_052]] | ||
|- | |- | ||
| | | 3 | ||
| | | 22 | ||
| | | (GPIO) / Camera D1 | ||
| [[# | | [[#TS-SOCKET|CN2_056]] | ||
|- | |- | ||
| | | 3 | ||
| | | 23 | ||
| | | (GPIO) / Camera D2 | ||
| [[# | | [[#TS-SOCKET|CN2_058]] | ||
|- | |- | ||
| | | 3 | ||
| | | 24 | ||
| | | (GPIO) / Camera D3 | ||
| [[# | | [[#TS-SOCKET|CN2_060]] | ||
|- | |- | ||
| | | 3 | ||
| | | 25 | ||
| | | (GPIO) / Camera D4 | ||
| [[# | | [[#TS-SOCKET|CN2_062]] | ||
|- | |- | ||
| | | 3 | ||
| | | 26 | ||
| | | (GPIO) / Camera D5 | ||
| [[# | | [[#TS-SOCKET|CN2_064]] | ||
|- | |- | ||
| | | 3 | ||
| | | 27 | ||
| | | (GPIO) / Camera D6 | ||
| [[# | | [[#TS-SOCKET|CN2_066]] | ||
|- | |- | ||
| | | 3 | ||
| | | 28 | ||
| | | (GPIO) / Camera D7 | ||
| [[# | | [[#TS-SOCKET|CN2_068]] | ||
|- | |- | ||
| | | 4 | ||
| | | 0 | ||
| | | POWER_FAIL<ref>Asserted when external power input falls below valid input range.</ref> | ||
| | | N/A | ||
|- | |- | ||
| | | 4 | ||
| | | 1 | ||
| | | [[#ZPU|ZPU IRQ]] | ||
| [[# | | [[#FPGA|FPGA]] | ||
|- | |- | ||
| | | 4 | ||
| | | 8 | ||
| ([[#Wi-Fi|Wi-Fi IRQ]]) / GPIO | |||
| [[# | | [[#Crossbar|FPGA Crossbar SPARE_4]] | ||
|- | |||
| [[# | |||
|} | |} | ||
< | <references/> |
Latest revision as of 17:12, 26 July 2019
Chip | Pin | Functions | Location |
---|---|---|---|
0 | 0 | (USB1 OTG ID) / GPIO | CN2_074 |
0 | 1 | (GPIO) / ADC input | CN2_012 |
0 | 8 | (PWM0) / ADC input / GPIO | CN1_057 |
0 | 9 | (PWM1) / ADC input / GPIO | CN2_091 |
0 | 10 | (Ethernet PHY power en.) / GPIO | CN2_046 |
0 | 11 | (I2S Master Clock) / GPIO | CN2_054 |
0 | 12 | (I2S TX Sync) / GPIO | CN2_038 |
0 | 13 | (I2S TX Bit Clock) / GPIO | CN2_036 |
0 | 14 | (I2S RX Data) / GPIO | CN2_042 |
0 | 15 | (I2S TX Data) / GPIO | CN2_040 |
0 | 16 | (Console UART TXD) / GPIO | CN2_093 / Microcontroller |
0 | 17 | (Console UART RXD) / GPIO | CN2_095 / Microcontroller |
0 | 18 | (GPIO) | FPGA Crossbar SPARE_1 |
0 | 19 | (GPIO) | FPGA Crossbar SPARE_2 |
0 | 20 | (UART1 TXD) / GPIO | CN2_082 |
0 | 21 | (UART1 RXD) / GPIO | CN2_084 |
0 | 22 | (CAN1 TX) / GPIO | CN1_071 |
0 | 23 | (CAN1 RX) / GPIO | CN1_069 |
0 | 24 | (UART2 TXD) / GPIO | FPGA Crossbar UART2_TXD |
0 | 25 | (UART2 RXD) / GPIO | FPGA Crossbar UART2_RXD |
0 | 26 | (UART2 CTS) / GPIO | FPGA Crossbar UART2_CTS |
0 | 27 | (UART2 RTS) / GPIO | FPGA Crossbar UART2_RTS |
0 | 28 | (UART3 TXD) / GPIO | FPGA Crossbar UART3_TXD |
0 | 29 | (UART3 RXD) / GPIO | FPGA Crossbar UART3_RXD |
0 | 30 | (UART4 TXD) / GPIO | CN2_090 |
0 | 31 | (UART4 RXD) / GPIO | CN2_092 |
2 | 0 | (GPIO) / LCD CLK | CN1_049 |
2 | 1 | (GPIO) / LCD DE | CN1_055 |
2 | 2 | (GPIO) / LCD HSYNC | CN1_051 |
2 | 3 | (GPIO) / LCD VSYNC | CN1_053 |
2 | 7 | (GPIO) / LCD D02 | CN1_028 |
2 | 8 | (GPIO) / LCD D03 | CN1_030 |
2 | 9 | (GPIO) / LCD D04 | CN1_032 |
2 | 10 | (GPIO) / LCD D05 | CN1_034 |
2 | 11 | (GPIO) / LCD D06 | CN1_038 |
2 | 12 | (GPIO) / LCD D07 | CN1_040 |
2 | 13 | (CAN0 TX) / GPIO | CN2_097 |
2 | 14 | (CAN0 RX) / GPIO | CN2_099 |
2 | 15 | (GPIO) / LCD D10 | CN1_023 |
2 | 16 | (GPIO) / LCD D11 | CN1_025 |
2 | 17 | (GPIO) / LCD D12 | CN1_027 |
2 | 18 | (GPIO) / LCD D13 | CN1_031 |
2 | 19 | (GPIO) / LCD D14 | CN1_033 |
2 | 20 | (GPIO) / LCD D15 | CN1_035 |
2 | 21 | (UART6 TXD) / GPIO | FPGA Crossbar UART6_TXD |
2 | 22 | (UART6 RXD) / GPIO | FPGA Crossbar UART6_RXD |
2 | 23 | (PWM4) / GPIO / LCD D18 | CN1_041 |
2 | 24 | (PWM5) / GPIO / LCD D19 | CN1_043 |
2 | 25 | (GPIO) / LCD D20 | CN1_045 |
2 | 26 | (GPIO) / LCD D21 | CN1_042 |
2 | 27 | (GPIO) / LCD D22 | CN1_044 |
2 | 28 | (GPIO) / LCD D23 | CN1_046 |
3 | 10 | (SPI2 Offboard CS#) / GPIO | CN2_065 / HD1_13 |
3 | 11 | (GPIO) | FPGA_RESET# |
3 | 12 | (SPI2 FPGA CS#) / GPIO | FPGA |
3 | 13 | (SPI2 CLK) / GPIO | CN2_071 / HD1_15 / FPGA |
3 | 14 | (SPI2 MOSI) / GPIO | CN2_067 / HD1_11 / FPGA |
3 | 15 | (SPI2 MISO) / GPIO | CN2_069 / HD1_9 / FPGA |
3 | 16 | (GPIO) | FPGA Crossbar SPARE_3 |
3 | 17 | (GPIO) / Camera MCLK | CN2_034 |
3 | 18 | (GPIO) / Camera PIXCLK | CN2_032 |
3 | 19 | (GPIO) / Camera VSYNC | CN2_072 |
3 | 20 | (GPIO) / Camera HSYNC | CN2_070 |
3 | 21 | (GPIO) / Camera D0 | CN2_052 |
3 | 22 | (GPIO) / Camera D1 | CN2_056 |
3 | 23 | (GPIO) / Camera D2 | CN2_058 |
3 | 24 | (GPIO) / Camera D3 | CN2_060 |
3 | 25 | (GPIO) / Camera D4 | CN2_062 |
3 | 26 | (GPIO) / Camera D5 | CN2_064 |
3 | 27 | (GPIO) / Camera D6 | CN2_066 |
3 | 28 | (GPIO) / Camera D7 | CN2_068 |
4 | 0 | POWER_FAIL[1] | N/A |
4 | 1 | ZPU IRQ | FPGA |
4 | 8 | (Wi-Fi IRQ) / GPIO | FPGA Crossbar SPARE_4 |
- ↑ Asserted when external power input falls below valid input range.