TS-4100 CPU DIO Table
From embeddedTS Manuals
The GPIO numbers in the table below are relevant to how the Linux references these numbers. The CPU documentation refers to bank and IO while Linux flattens this out to one number space.
GPIO Number | Name | REMOVE | Functions [1] | Location |
---|---|---|---|---|
16 | CONSOLE_TXD | (Console UART) / GPIO | CN2_093 / Microcontroller | |
17 | CONSOLE_RXD | (Console UART) / GPIO | CN2_095 / Microcontroller | |
18 | SPARE_1 | (GPIO) | FPGA Crossbar | |
19 | SPARE_2 | (GPIO) | FPGA Crossbar | |
20 | UART2_TXD | (UART) / GPIO | CN2_082 | |
21 | UART2_RXD | (UART) / GPIO | CN2_084 | |
CAN_2_TXD | UART2_CTS_B | 22 | #CAN | CN1_071 |
CAN_2_RXD | UART2_RTS_B | 23 | #CAN | CN1_069 |
UART3_RXD | UART3_RX_DATA | 25 | #COM_Ports | FPGA Crossbar (Default Bluetooth RX) |
UART3_TXD | UART3_TX_DATA | 24 | #COM_Ports | FPGA Crossbar (Default Bluetooth TX) |
UART3_CTS# | UART3_CTS_B | 26 | #COM_Ports | FPGA Crossbar (Default Bluetooth CTS) |
UART3_RTS# | UART3_RTS_B | 27 | #COM_Ports | FPGA Crossbar (Default Bluetooth RTS) |
UART4_RXD | UART4_RX_DATA | 29 | #COM_Ports | FPGA Crossbar (Default CN2_080) |
UART4_TXD | UART4_TX_DATA | 28 | #COM_Ports | FPGA Crossbar (Default CN2_078) |
UART5_RXD | UART5_RX_DATA | 31 | #COM_Ports | CN2_092 |
UART5_TXD | UART5_TX_DATA | 30 | #COM_Ports | CN2_090 |
AUD_RXD | JTAG_TCK | 14 | #I2S / #JTAG | CN2_042 |
AUD_CLK | JTAG_TDI | 13 | #I2S / #JTAG | CN2_036 |
AUD_FRM | JTAG_TDO | 12 | #I2S / #JTAG | CN2_038 |
AUD_MCLK | JTAG_TMS | 11 | #I2S / #JTAG | CN2_054 |
AUD_TXD | JTAG_TRST_B | 15 | #I2S / #JTAG | CN2_040 |
EN_ETH_PHY_PWR | JTAG_MOD | 10 | Eth PHY enable / #JTAG | CN2_046 |
CAM_D_0 | CSI_DATA00 | 117 | #Camera Interface / GPIO | CN2_052 |
CAM_D_1 | CSI_DATA01 | 118 | #Camera Interface / GPIO | CN2_056 |
CAM_D_2 | CSI_DATA02 | 119 | #Camera Interface / GPIO | CN2_058 |
CAM_D_3 | CSI_DATA03 | 120 | #Camera Interface / GPIO | CN2_060 |
CAM_D_4 | CSI_DATA04 | 121 | #Camera Interface / GPIO | CN2_062 |
CAM_D_5 | CSI_DATA05 | 122 | #Camera Interface / GPIO | CN2_064 |
CAM_D_6 | CSI_DATA06 | 123 | #Camera Interface / GPIO | CN2_066 |
CAM_D_7 | CSI_DATA07 | 124 | #Camera Interface / GPIO | CN2_068 |
CAM_HSYNC | CSI_HSYNC | 116 | #Camera Interface / GPIO | CN2_070 |
CAM_MCLK | CSI_MCLK | 113 | #Camera Interface / GPIO | CN2_034 |
CAM_PIX_CLK | CSI_PIXCLK | 114 | #Camera Interface / GPIO | CN2_032 |
CAM_VSYNC | CSI_VSYNC | 115 | #Camera Interface / GPIO | CN2_072 |
USB_OTG1_ID | GPIO1_IO00 | 0 | USB1 OTG ID | CN2_074 / USB_OTG_5V power switch |
GPIO_1_ADC | GPIO1_IO01 | 1 | #ADC / GPIO | CN2_012 |
EN_OTG1_5V | GPIO1_IO04 | 4 | USB OTG switch 5V [2] | Onboard Regulator |
SD_VSEL_1.8V | GPIO1_IO05 | 5 | SD 1.8V switch [3] | Onboard Regulator |
LCD_PWM_ADC8 | GPIO1_IO08 | 8 | #PWM, #ADC, GPIO | CN1_057 |
GPIO_9_ADC | GPIO1_IO09 | 9 | #ADC, GPIO | CN2_091 |
POWER_FAIL | SNVS_TAMPER0 | 128 | Power Notification [4] | Onboard PWR Monitor |
FPGA_IRQ | SNVS_TAMPER1 | 129 | #FPGA | FPGA Crossbar (Default NC) |
EN_FPGA_PWR | SNVS_TAMPER2 | 130 | FPGA 3.3V switch | Onboard FET |
GPIO_DVFS | SNVS_TAMPER3 | 131 | CPU DVFS [5] | Onboard Regulator |
JTAG_FPGA_TDO | SNVS_TAMPER4 | 132 | FPGA JTAG | FPGA JTAG pin |
JTAG_FPGA_TDI | SNVS_TAMPER5 | 133 | FPGA JTAG | FPGA JTAG pin |
JTAG_FPGA_TMS | SNVS_TAMPER6 | 134 | FPGA JTAG | FPGA JTAG pin |
JTAG_FPGA_TCK | SNVS_TAMPER7 | 135 | FPGA JTAG | FPGA JTAG pin |
SPARE_4 | SNVS_TAMPER8 | 136 | GPIO | FPGA Crossbar (Default WIFI IRQ) |
EN_SD_POWER | SNVS_TAMPER9 | 137 | SD power enable | Onboard Regulator |
I2C_3_DAT | LCD_DATA00 | 69 | #I2C [6] | CN2_030, HD1 pin 10 |
I2C_3_CLK | LCD_DATA01 | 70 | #I2C [6] | CN2_028, HD1 pin 8 |
LCD_D02 | LCD_DATA02 | 71 | #Parallel LCD Interface, GPIO | CN1_028 |
LCD_D03 | LCD_DATA03 | 72 | #Parallel LCD Interface, GPIO | CN1_030 |
LCD_D04 | LCD_DATA04 | 73 | #Parallel LCD Interface, GPIO | CN1_032 |
LCD_D05 | LCD_DATA05 | 74 | #Parallel LCD Interface, GPIO | CN1_034 |
LCD_D06 | LCD_DATA06 | 75 | #Parallel LCD Interface, GPIO | CN1_038 |
LCD_D07 | LCD_DATA07 | 76 | #Parallel LCD Interface, GPIO | CN1_040 |
CAN_1_TXD | LCD_DATA08 | 77 | #CAN, GPIO | CN2_097 |
CAN_1_RXD | LCD_DATA09 | 78 | #CAN, GPIO | CN2_099 |
LCD_D10 | LCD_DATA10 | 79 | #Parallel LCD Interface, GPIO | CN1_023 |
LCD_D11 | LCD_DATA11 | 80 | #Parallel LCD Interface, GPIO | CN1_025 |
LCD_D12 | LCD_DATA12 | 81 | #Parallel LCD Interface, GPIO | CN1_027 |
LCD_D13 | LCD_DATA13 | 82 | #Parallel LCD Interface, GPIO | CN1_031 |
LCD_D14 | LCD_DATA14 | 83 | #Parallel LCD Interface, GPIO | CN1_033 |
LCD_D15 | LCD_DATA15 | 84 | #Parallel LCD Interface, GPIO | CN1_035 |
UART7_TXD | LCD_DATA16 | 85 | #COM_Ports | FPGA Crossbar (Default CN2_86) |
UART7_RXD | LCD_DATA17 | 86 | #COM_Ports | FPGA Crossbar (Default CN2_88) |
LCD_D18 | LCD_DATA18 | 87 | #Parallel LCD Interface, GPIO | CN1_041 |
LCD_D19 | LCD_DATA19 | 88 | #Parallel LCD Interface, GPIO | CN1_043 |
LCD_D20 | LCD_DATA20 | 89 | #Parallel LCD Interface, GPIO | CN1_045 |
LCD_D21 | LCD_DATA21 | 90 | #Parallel LCD Interface, GPIO | CN1_042 |
LCD_D22 | LCD_DATA22 | 91 | #Parallel LCD Interface, GPIO | CN1_044 |
LCD_D23 | LCD_DATA23 | 92 | #Parallel LCD Interface, GPIO | CN1_046 |
LCD_PIX_CLK | LCD_CLK | 64 | #Parallel LCD Interface, GPIO | CN1_049 |
LCD_DE | LCD_ENABLE | 65 | #Parallel LCD Interface, GPIO | CN1_055 |
LCD_HSYNC | LCD_HSYNC | 66 | #Parallel LCD Interface, GPIO | CN1_051 |
LCD_VSYNC | LCD_VSYNC | 67 | #Parallel LCD Interface, GPIO | CN1_053 |
FPGA_RESET# | NAND_WP_B | 107 | Used to reset on reload | Onboard FPGA |
SPI_3_FPGA_CS# | NAND_READY_B | 108 | FPGA SPI CS | Onboard FPGA |
SPI_3_CLK | NAND_CE0_B | 109 | #SPI | CN2_071, HD1 pin 15 |
SPI_3_MOSI | NAND_CE1_B | 110 | #SPI | CN2_067, HD1 pin 11 |
SPI_3_MISO | NAND_CLE | 111 | #SPI | CN2_069, HD1 pin 9 |
SPARE_3 | NAND_DQS | 112 | GPIO | FPGA Crossbar (Default NC) |
SPI_3_OFF_BD_CS# | NAND_ALE | 106 | #SPI | CN2_065, HD1 pin 13 |
- ↑ Common functions for the pin. Default kernel function is denoted with parenthesis "()"
- ↑ TODO
- ↑ This is handled automatically by the kernel after negotiating the capabilities of the connected card. Switching to 1.8V on a 3.3V card can cause damage.
- ↑ This will assert high when power is disconnected and the system and the board is running off supercaps if populated.
- ↑ Under almost all cases this should be maintained by the kernel
- ↑ 6.0 6.1 This i2c bus is used to access all of the FPGA GPIO and typically should not be repurposed as GPIO.