TS-4100 FPGA

The TS-4100 FPGA provides additional DIO (that are connected to a Crossbar MUX), some miscellaneous system peripherals, and the 32-bit ZPU microcontroller. The FPGA is a Lattice MachXO2.

See the GPIO section for information on accessing the FPGA DIO.

The FPGA registers are accessed via an I2C bus. The FPGA emulates an I2C EEPROM, allowing for a simple and standard communication protocol to the FPGA. The FPGA is available at I2C addresses 0x28-0x2F. Accessing individual registers requires a chip address write, a 16-bit register address write, then 8-bit data values. A read or write stream can occur; every every byte read or written the internal register pointer moves to the next sequential register. This allows for reading or writing multiple registers without having to re-issue the chip and register address sequence.

We provide a simple access mechanism to the FPGA using the 'tshwctl' utility. This utility can read or write arbitrary registers, return some information about the FPGA, as well as configure the Crossbar MUX. Sources for 'tshwctl' and other utilities specific to the TS-4100 can be found in the TS-4100 utilities github repository.

The register map is broken in to a few different sections:

Section	Address	Bits	Description
GPIOn	0x0000-0x00FF	7:3	Reserved (Write 0)
		2	GPIOn Input Data
		1	GPIOn Output Data
		0	GPIOn Output Enable
CROSSBARn	0x0080-0x00FF	7	CROSSBARn GPIO mode
		6:0	CROSSBARn Value
BANKn	0x0100-0x010F	7:0	GPIOn Bank Input
	0x0110-0x011F	7:0	GPIOn Bank Output Data
	0x0120-0x012F	7:0	GPIOn Bank Output Enable
Misc	0x0130	7:0	Model Number MSB (0x41)
	0x0131	7:0	Model Number LSB (0x00)
	0x0132	7:0	FPGA Rev
	0x0133-0x1FFF	7:0	Reserved
ZPU	0x1FFF-0x2FFF	7:0	ZPU RAM access

GPIOn

Registers 0x00-0x7F provide DIO control. The GPIO can be manipulated via the sysfs GPIO interface, information on this can be found in the GPIO section which is the recommended way to manipulate these pins. Each register in this section manipulates a different DIO pin. See the "FPGA I/O" table below for the register offset for this section. For example, to set "DIO_1" to a low output, the value 0x1 would be written to FPGA register 0x26 (the I/O number of "DIO_1").

Note:

The sysfs GPIO interface is recommended because it guarantees a clean state transition. When setting a GPIOn register, modifying multiple bits simultaneously creates a race condition between the output and output enable bits. This may result in a short glitch on the pin as it transitions. The sysfs GPIO driver will only manipulate a single bit at a time resulting in a clean and guaranteed transition.

CROSSBARn

Registers 0x80-0xFF provide control for the Crossbar MUX. Like GPIOn above, each register represents a single DIO pin which are listed in the "FPGA I/O" table below. In order to change the MUX setting of any individual pin, its corresponding register is written to. For example, to set "UARTA_TXD" to output the data from "UART2_TXD", write the value of 0x5 (the I/O number of "UART2_TXD") to register (0x80+0x21) = 0xA1 (the I/O number of "UARTA_TXD" plus the CROSSBARn section starting register). The 'tshwctl' utility provides an easy abstraction for this process. See the Crossbar MUX section for more information on this process as well as a breakdown of Crossbar assignments.

BANKn

Registers 0x100-0x12F provide banked DIO access. The banked DIO allows for manipulating multiple pins simultaneously. Each bank register has 8 bits that represent 8 DIO pins. There are 48 bank registers total, 16 for GPIO input, 16 for GPIO output, and 16 for GPIO output enable. The bank and bit position of any given DIO listed in the "FPGA I/O" table below can be calculated by dividing the I/O number by 8 to get the bank number and then taking the modulus of that same calculation to get the bit position. The BANKn registers are not intended for normal use and exist to allow the ZPU to readily manipulate GPIO pins.

Misc

Registers 0x130-0x132 provide the model number and FPGA software revision. Registers 0x133-0x1FFF are reserved.

ZPU

Registers 0x2000-0x3FFF are RAM intended for use by the ZPU. Normally unused unless the ZPU is loaded and run, these registers can be used for volatile storage if wanted.

FPGA I/O

I/O Number	Signal name	Crossbar support	Direction
1	SPARE_1	Y	I/O
2	SPARE_2	Y	I/O
5	UART2_TXD	Y	Input
6	UART2_RTS	Y	Input
7	UART3_TXD	Y	Input
8	UART6_TXD	Y	Input
9	UART2_RXD	Y	Output
10	UART2_CTS	Y	Output
11	UART3_RXD	Y	Output
12	UART6_RXD	Y	Output
13	WIFI_RXD	Y	Input
14	WIFI_RTS	Y	Input
15	WIFI_IRQ	Y	Input
16	WIFI_TXD	Y	Output
17	WIFI_CTS	Y	Output
18	ZPU_BREAK	N	Input
19	ZPU_RESET	N	Output
20	EN_WIFI_PWR	DIO	Output
21	WIFI_RESET	DIO	Output
22	EN_USB_HOST_5V	DIO	Output
23	EN_LCD_3V3	DIO	Output
24	EN_SD_POWER	DIO	Output
25	OFF_BD_RESET	DIO	Output
26	EN_SW_3V3	DIO	Output
27	GREEN_LED	DIO	Output
28	RED_LED	DIO	Output
29	UARTA_RXD	UART+Spares	I/O
30	UARTB_RXD	UART+Spares	I/O
31	UARTC_RXD	UART+Spares	I/O
32	UARTD_RXD	UART+Spares	I/O
33	UARTA_TXD	UART+Spares	I/O
34	UARTB_TXD	UART+Spares	I/O
35	UARTC_TXD	UART+Spares	I/O
36	UARTD_TXD	UART+Spares	I/O
37	DIO_0	UART+SPARE pins	I/O
38	DIO_1	UART+SPARE pins	I/O
39	DIO_2	UART+SPARE pins	I/O
40	DIO_3	UART+SPARE pins	I/O
41	DIO_4	UART+SPARE pins	I/O
42	DIO_5	UART+SPARE pins	I/O
43	DIO_6	UART+SPARE pins	I/O
44	DIO_7	UART+SPARE pins	I/O
45	DIO_8	UART+SPARE pins	I/O
46	DIO_9	UART+SPARE pins	I/O
47	DIO_10	UART+SPARE pins	I/O
48	DIO_11	UART+SPARE pins	I/O
49	DIO_12	UART+SPARE pins	I/O
50	DIO_13	UART+SPARE pins	I/O
51	DIO_14	UART+SPARE pins	I/O
52	DIO_15	UART+SPARE pins	I/O
53	DIO_16	UART+SPARE pins	I/O
54	DIO_17	UART+SPARE pins	I/O
55	DIO_18	UART+SPARE pins	I/O
56	DIO_19	UART+SPARE pins	I/O
57	DIO_20	UART+SPARE pins	I/O
58	DIO_21	UART+SPARE pins	I/O
59	DIO_22	UART+SPARE pins	I/O
60	DIO_23	UART+SPARE pins	I/O
61	DIO_24	UART+SPARE pins	I/O
62	DIO_25	UART+SPARE pins	I/O
63	DIO_26	UART+SPARE pins	I/O
64	DIO_27	UART+SPARE pins	I/O
65	DIO_28	UART+SPARE pins	I/O
66	DIO_29	UART+SPARE pins	I/O
67	DIO_30	UART+SPARE pins	I/O
68	DIO_31	UART+SPARE pins	I/O
69	DIO_32	UART+SPARE pins	I/O
70	DIO_33	UART+SPARE pins	I/O
71	DIO_34	UART+SPARE pins	I/O
72	DIO_35	UART+SPARE pins	I/O
73	DIO_36	UART+SPARE pins	I/O
74	DIO_37	UART+SPARE pins	I/O
75	DIO_38	UART+SPARE pins	I/O
76	DIO_39	UART+SPARE pins	I/O
77	DIO_40	UART+SPARE pins	I/O
78	DIO_41	UART+SPARE pins	I/O
79	DIO_42	UART+SPARE pins	I/O
80	DIO_43	UART+SPARE pins	I/O
81	DIO_44	UART+SPARE pins	I/O
82	DIO_45	UART+SPARE pins	I/O
83	DIO_46	UART+SPARE pins	I/O