TS-4100 FPGA: Difference between revisions
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The FPGA is available at I2C addresses 0x28-0x2f. First write the address which is 16-bits, followed by the data which is 8-bits. | The FPGA is available at I2C addresses 0x28-0x2f. First write the address which is 16-bits, followed by the data which is 8-bits. | ||
The first registers 0-127 are used to control the GPIO. Use the IO offsets below from 0 to set the pin state. | |||
{| class="wikitable sortable" | {| class="wikitable sortable" | ||
|+ GPIO Register Description | |||
|- | |- | ||
! Bits | ! Bits | ||
! Description | ! Description | ||
|- | |- | ||
| 7:3 | | 7:3 | ||
| Reserved (Write 0) | | Reserved (Write 0) | ||
Line 28: | Line 21: | ||
| 0 | | 0 | ||
| Output Enable | | Output Enable | ||
|} | |||
Registers 128-255 control the crossbar for the various pins. Use address 128 + IO number for the offset. | |||
{| class="wikitable sortable" | |||
|+ Crossbar Register Description | |||
|- | |||
! Bits | |||
! Description | |||
|- | |||
| 7 | |||
| GPIO mode (overrides crossbar) | |||
|- | |||
| 6:0 | |||
| Crossbar Value | |||
|} | |||
The two registers above use this table for the offset. The crossbar support shows whether it can be mapped with the crossbar register above. The direction column describes if the IO is direction locked, or GPIO if they can be either. The directions are from the perspective of the FPGA, so for example UART TX from the CPU will be an input to the FPGA. The input data from that UART can be mapped to other pins offboard to pass through the data anywhere. | |||
{| class="wikitable sortable" | |||
|+ FPGA IO | |||
|- | |||
! IO Number | |||
! Pad | |||
! Crossbar support | |||
! Direction | |||
|- | |||
| 1 | |||
| UART3_TXD (ttymxc2) | |||
| Y | |||
| Input | |||
|- | |||
| 2 | |||
| UART3_RXD (ttymxc2) | |||
| Y | |||
| Output | |||
|- | |||
| 3 | |||
| UART3_RTSn (ttymxc2) | |||
| Y | |||
| Input | |||
|- | |||
| 4 | |||
| UART3_CTSn (ttymxc2) | |||
| Y | |||
| Output | |||
|- | |||
| 5 | |||
| UART4_TXD (ttymxc3) | |||
| Y | |||
| Input | |||
|- | |||
| 6 | |||
| UART4_RXD (ttymxc3) | |||
| Y | |||
| Output | |||
|- | |||
| 7 | |||
| UART7_TXD (ttymxc6) | |||
|- | |||
| 8 | |||
| UART7_RXD (ttymxc6) | |||
|- | |||
| 9 | |||
| SPARE_1 (UART1_CTS_B) | |||
| Y | |||
| GPIO | |||
|- | |||
| 10 | |||
| SPARE_2 (UART1_RTS_B) | |||
| Y | |||
| GPIO | |||
|- | |||
| 11 | |||
| WIFI_RESET | |||
| N | |||
| Output | |||
|- | |||
| 12 | |||
| EN_WIFI_PWR | |||
| N | |||
| Output | |||
|- | |||
| 13 | |||
| WIFI_TXD | |||
| Y | |||
| Output | |||
|- | |||
| 14 | |||
| WIFI_RXD | |||
| Y | |||
| Output | |||
|- | |||
| 15 | |||
| WIFI_RTS | |||
| Y | |||
| Input | |||
|- | |||
| 16 | |||
| WIFI_CTS | |||
| Y | |||
| Output | |||
|- | |||
| 17 | |||
| UART_A_TXD | |||
| Y | |||
| Output | |||
|- | |||
| 18 | |||
| UART_A_RXD | |||
| Y | |||
| Input | |||
|- | |||
| 19 | |||
| UART_B_TXD | |||
| Y | |||
| Output | |||
|- | |||
| 20 | |||
| UART_B_RXD | |||
| Y | |||
| Input | |||
|- | |||
| 21 | |||
| UART_C_TXD | |||
| Y | |||
| Output | |||
|- | |||
| 22 | |||
| UART_C_RXD | |||
| Y | |||
| Input | |||
|- | |||
| 23 | |||
| UART_D_TXD | |||
| Y | |||
| Output | |||
|- | |||
| 24 | |||
| UART_D_RXD | |||
| Y | |||
| Input | |||
|- | |||
| 25 | |||
| EN_HOST_USB_5V | |||
| N | |||
| Output | |||
|- | |||
| 26 | |||
| EN_LCD_3.3V | |||
| N | |||
| Output | |||
|- | |||
| 27 | |||
| EN_SD_POWER | |||
| N | |||
| Output | |||
|- | |||
| 28 | |||
| OFF_BD_RESET | |||
| N | |||
| Output | |||
|- | |||
| 29 | |||
| EN_SW_3.3V | |||
| N | |||
| Output | |||
|- | |||
| 30 | |||
| GREEN_LED | |||
| N | |||
| Output | |||
|- | |||
| 31 | |||
| RED_LED | |||
| N | |||
| Output | |||
|} | |} |
Revision as of 12:02, 23 February 2016
The TS-4100 FPGA registers are accessed over I2C. The /sys/class/gpio driver provides access to the IO using these registers. See the #GPIO section for more information on the recommended method for IO access.
The FPGA is available at I2C addresses 0x28-0x2f. First write the address which is 16-bits, followed by the data which is 8-bits.
The first registers 0-127 are used to control the GPIO. Use the IO offsets below from 0 to set the pin state.
Bits | Description |
---|---|
7:3 | Reserved (Write 0) |
2 | Input Data |
1 | Output Data |
0 | Output Enable |
Registers 128-255 control the crossbar for the various pins. Use address 128 + IO number for the offset.
Bits | Description |
---|---|
7 | GPIO mode (overrides crossbar) |
6:0 | Crossbar Value |
The two registers above use this table for the offset. The crossbar support shows whether it can be mapped with the crossbar register above. The direction column describes if the IO is direction locked, or GPIO if they can be either. The directions are from the perspective of the FPGA, so for example UART TX from the CPU will be an input to the FPGA. The input data from that UART can be mapped to other pins offboard to pass through the data anywhere.
IO Number | Pad | Crossbar support | Direction |
---|---|---|---|
1 | UART3_TXD (ttymxc2) | Y | Input |
2 | UART3_RXD (ttymxc2) | Y | Output |
3 | UART3_RTSn (ttymxc2) | Y | Input |
4 | UART3_CTSn (ttymxc2) | Y | Output |
5 | UART4_TXD (ttymxc3) | Y | Input |
6 | UART4_RXD (ttymxc3) | Y | Output |
7 | UART7_TXD (ttymxc6) | ||
8 | UART7_RXD (ttymxc6) | ||
9 | SPARE_1 (UART1_CTS_B) | Y | GPIO |
10 | SPARE_2 (UART1_RTS_B) | Y | GPIO |
11 | WIFI_RESET | N | Output |
12 | EN_WIFI_PWR | N | Output |
13 | WIFI_TXD | Y | Output |
14 | WIFI_RXD | Y | Output |
15 | WIFI_RTS | Y | Input |
16 | WIFI_CTS | Y | Output |
17 | UART_A_TXD | Y | Output |
18 | UART_A_RXD | Y | Input |
19 | UART_B_TXD | Y | Output |
20 | UART_B_RXD | Y | Input |
21 | UART_C_TXD | Y | Output |
22 | UART_C_RXD | Y | Input |
23 | UART_D_TXD | Y | Output |
24 | UART_D_RXD | Y | Input |
25 | EN_HOST_USB_5V | N | Output |
26 | EN_LCD_3.3V | N | Output |
27 | EN_SD_POWER | N | Output |
28 | OFF_BD_RESET | N | Output |
29 | EN_SW_3.3V | N | Output |
30 | GREEN_LED | N | Output |
31 | RED_LED | N | Output |