TS-4100 FPGA: Difference between revisions

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The FPGA is available at I2C addresses 0x28-0x2f.  First write the address which is 16-bits,  followed by the data which is 8-bits.
The FPGA is available at I2C addresses 0x28-0x2f.  First write the address which is 16-bits,  followed by the data which is 8-bits.


The first registers 0-127 are used to control the GPIO.  Use the IO offsets below from 0 to set the pin state.
The first registers 0-127 are used to control the GPIO.  Registers 128-255 control the crossbar for the various pins.  Use the IO offsets int the second table for the GPIO and CROSSBAR registers.
 
{| class="wikitable"
{| class="wikitable"
|+ GPIO Register Description
|+ GPIO_n Register
|-
|-
! Address
! Bits
! Bits
! Description
! Description
|-
|-
| 127:0 | rowspan=4
| 7:3
| 7:3
| Reserved (Write 0)
| Reserved (Write 0)
|-
|-
| 2
| 2
| Input Data
| GPIOn Input Data
|-
|-
| 1
| 1
| Output Data
| GPIOn Output Data
|-
|-
| 0
| 0
| Output Enable  
| GPIOn Output Enable  
|}
 
Registers 128-255 control the crossbar for the various pins.  Use address 128 + IO number for the offset.
 
{| class="wikitable"
|+ Crossbar Register Description
|-
! Bits
! Description
|-
|-
| rowspan=2 | 128:255
| 7
| 7
| GPIO mode (overrides crossbar)
| CROSSBARn GPIO mode
|-
|-
| 6:0
| 6:0
| Crossbar Value
| CROSSBARn Value
|-
| 271:256
| 7:0
| GPIOn Bank Input
|-
| 287:272
| 7:0
| GPIOn Bank Output Data
|-
| 288:303
| 7:0
| GPIOn Bank Output Enable (1=out)
|-
| 304
| 7:0
| Model Number MSB (0x41)
|-
| 305
| 7:0
| Model Number LSB (0x00)
|-
| 306
| 7:0
| FPGA Rev
|-
| 8191:307
| 7:0
| Reserved
|-
| 16384:8192
| 7:0
| [[#ZPU|ZPU RAM access]]
|}
|}
<References />
In the above table the GPIO, Crossbar, and Bank registers will use the following IO.  The bank registers should divide the IO number by 8 to get the offset, and use the modulus to get the bit number.


The two registers above use this table for the offset.  The crossbar support shows whether it can be mapped with the crossbar register above.  The direction column describes if the IO is direction locked, or GPIO if they can be either.  The directions are from the perspective of the FPGA, so for example UART TX from the CPU will be an input to the FPGA.  The input data from that UART can be mapped to other pins offboard to pass through the data anywhere.
{| class="wikitable sortable"
{| class="wikitable sortable"
|+ FPGA IO
|+ FPGA IO
Line 48: Line 77:
|-
|-
| 1
| 1
| UART3_TXD (ttymxc2)
| UART3_TXD_PAD (ttymxc2)
| Y
| Y
| Input
| Input
|-
|-
| 2
| 2
| UART3_RXD (ttymxc2)
| UART3_RTS_PADn (ttymxc2)
| Y
| Y
| Output
| Input
|-
|-
| 3
| 3
| UART3_RTSn (ttymxc2)
| UART4_TXD_PAD (ttymxc3)
| Y
| Y
| Input
| Input
|-
|-
| 4
| 4
| UART3_CTSn (ttymxc2)
| UART7_TXD_PAD (ttymxc6)
| Y
| Y
| Output
| Input
|-
|-
| 5
| 5
| UART4_TXD (ttymxc3)
| UART_A_RXD_PAD
| Y
| Y
| Input
| Input
|-
|-
| 6
| 6
| UART4_RXD (ttymxc3)
| UART_B_RXD_PAD
| Y
| Y
| Output
| Input
|-
|-
| 7
| 7
| UART7_TXD (ttymxc6)
| UART_C_RXD_PAD
| Y
| Y
| Input
| Input
|-
|-
| 8
| 8
| UART7_RXD (ttymxc6)
| UART_D_RXD_PAD
| Y
| Y
| Output
| Input
|-
|-
| 9
| 9
| SPARE_1 (UART1_CTS_B)
| SPARE_1_PAD
| Y
| Y
| GPIO
| GPIO
|-
|-
| 10
| 10
| SPARE_2 (UART1_RTS_B)
| SPARE_2_PAD
| Y
| Y
| GPIO
| GPIO
|-
|-
| 11
| 11
| WIFI_RESET
| UART_3_RXD_PAD (ttymxc2)
| N
| DIO+WIFI
| Output
| Output
|-
|-
| 12
| 12
| EN_WIFI_PWR
| UART_3_CTS_PADN (ttymxc2)
| N
| DIO+WIFI
| Output
| Output
|-
|-
| 13
| 13
| WIFI_TXD
| UART4_RXD_PADN (ttymxc3)
| Y
| DIO+WIFI
| Output
| Output
|-
|-
| 14
| 14
| WIFI_RXD
| UART7_RXD_PAD (ttymxc6)
| Y
| DIO+WIFI
| Output
| Output
|-
|-
| 15
| 15
| WIFI_RTS
| UART_A_TXD_PAD
| Y
| DIO+WIFI
| Input
| Output
|-
|-
| 16
| 16
| WIFI_CTS
| UART_B_TXD_PAD
| Y
| DIO+WIFI
| Output
| Output
|-
|-
| 17
| 17
| UART_A_TXD
| UART_C_TXD_PAD
| Y
| DIO+WIFI
| Output
| Output
|-
|-
| 18
| 18
| UART_A_RXD
| UART_D_TXD_PAD
| Y
| DIO+WIFI
| Input
| Output
|-
|-
| 19
| 19
| UART_B_TXD
| WIFI_TXD_PAD
| Y
| DIO+WIFI
| Output
| Output
|-
|-
| 20
| 20
| UART_B_RXD
| WIFI_CTS_PAD
| Y
| DIO+WIFI
| Input
| Output
|-
|-
| 21
| 21
| UART_C_TXD
| [[#ZPU|ZPU_BREAK]]
| Y
| N
| Output
| Input
|-
|-
| 22
| 22
| UART_C_RXD
| [[#ZPU|ZPU_RESET]]
| Y
| N
| Input
| Output
|-
|-
| 23
| 23
| UART_D_TXD
| EN_WIFI_PWR_PAD {{Note|The WIFI driver toggles this automatically.  There should be no need to manually control this pin for power savings.}}
| Y
| N
| Output
| Output
|-
|-
| 24
| 24
| UART_D_RXD
| WIFI_RESET_PAD
| Y
| N
| Input
| Output
| 25
|-
|-
| 25
| 25
| EN_HOST_USB_5V
| EN_USB_HOST_5V_PAD
| N
| N
| Output
| Output
|-
|-
| 26
| 26
| EN_LCD_3.3V
| EN_LCD_3V3_PAD
| N
| N
| Output
| Output
|-
|-
| 27
| 27
| EN_SD_POWER
| EN_SD_POWER_PAD
| N
| N
| Output
| Output
|-
|-
| 28
| 28
| OFF_BD_RESET
| OFF_BD_RESET_PADN
| N
| N
| Output
| Output
|-
|-
| 29
| 29
| EN_SW_3.3V
| EN_SW_3V3_PADN
| N
| N
| Output
| Output
|-
|-
| 30
| 30
| GREEN_LED
| GREEN_LED_PADN
| N
| N
| Output
| Output
|-
|-
| 31
| 31
| RED_LED
| RED_LED_PADN
| N
| N
| Output
| Output
|-
| 78:32
| DIO_PAD[46:0]
| UART+SPARE pins
| Output
|-
| 79
| WIFI_RXD_PAD
| Y
| Input
|-
| 80
| WIFI_RTS_PAD
| Y
| Input
|}
|}

Revision as of 17:47, 25 February 2016

The TS-4100 FPGA registers are accessed over I2C. The /sys/class/gpio driver provides access to the IO using these registers. See the #GPIO section for more information on the recommended method for IO access.

The FPGA is available at I2C addresses 0x28-0x2f. First write the address which is 16-bits, followed by the data which is 8-bits.

The first registers 0-127 are used to control the GPIO. Registers 128-255 control the crossbar for the various pins. Use the IO offsets int the second table for the GPIO and CROSSBAR registers.

GPIO_n Register
Address Bits Description
rowspan=4 7:3 Reserved (Write 0)
2 GPIOn Input Data
1 GPIOn Output Data
0 GPIOn Output Enable
128:255 7 CROSSBARn GPIO mode
6:0 CROSSBARn Value
271:256 7:0 GPIOn Bank Input
287:272 7:0 GPIOn Bank Output Data
288:303 7:0 GPIOn Bank Output Enable (1=out)
304 7:0 Model Number MSB (0x41)
305 7:0 Model Number LSB (0x00)
306 7:0 FPGA Rev
8191:307 7:0 Reserved
16384:8192 7:0 ZPU RAM access


In the above table the GPIO, Crossbar, and Bank registers will use the following IO. The bank registers should divide the IO number by 8 to get the offset, and use the modulus to get the bit number.

FPGA IO
IO Number Pad Crossbar support Direction
1 UART3_TXD_PAD (ttymxc2) Y Input
2 UART3_RTS_PADn (ttymxc2) Y Input
3 UART4_TXD_PAD (ttymxc3) Y Input
4 UART7_TXD_PAD (ttymxc6) Y Input
5 UART_A_RXD_PAD Y Input
6 UART_B_RXD_PAD Y Input
7 UART_C_RXD_PAD Y Input
8 UART_D_RXD_PAD Y Input
9 SPARE_1_PAD Y GPIO
10 SPARE_2_PAD Y GPIO
11 UART_3_RXD_PAD (ttymxc2) DIO+WIFI Output
12 UART_3_CTS_PADN (ttymxc2) DIO+WIFI Output
13 UART4_RXD_PADN (ttymxc3) DIO+WIFI Output
14 UART7_RXD_PAD (ttymxc6) DIO+WIFI Output
15 UART_A_TXD_PAD DIO+WIFI Output
16 UART_B_TXD_PAD DIO+WIFI Output
17 UART_C_TXD_PAD DIO+WIFI Output
18 UART_D_TXD_PAD DIO+WIFI Output
19 WIFI_TXD_PAD DIO+WIFI Output
20 WIFI_CTS_PAD DIO+WIFI Output
21 ZPU_BREAK N Input
22 ZPU_RESET N Output
23 EN_WIFI_PWR_PAD
Note: The WIFI driver toggles this automatically. There should be no need to manually control this pin for power savings.
N Output
24 WIFI_RESET_PAD N Output 25
25 EN_USB_HOST_5V_PAD N Output
26 EN_LCD_3V3_PAD N Output
27 EN_SD_POWER_PAD N Output
28 OFF_BD_RESET_PADN N Output
29 EN_SW_3V3_PADN N Output
30 GREEN_LED_PADN N Output
31 RED_LED_PADN N Output
78:32 DIO_PAD[46:0] UART+SPARE pins Output
79 WIFI_RXD_PAD Y Input
80 WIFI_RTS_PAD Y Input
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