TS-4100 FPGA: Difference between revisions
From embeddedTS Manuals
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In the above table the GPIO, Crossbar, and Bank registers will use the following IO. The bank registers should divide the IO number by 8 to get the offset, and use the modulus to get the bit number. | In the above table the GPIO, Crossbar, and Bank registers will use the following IO. The bank registers should divide the IO number by 8 to get the offset, and use the modulus to get the bit number. | ||
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Revision as of 17:48, 25 February 2016
The TS-4100 FPGA registers are accessed over I2C. The /sys/class/gpio driver provides access to the IO using these registers. See the #GPIO section for more information on the recommended method for IO access.
The FPGA is available at I2C addresses 0x28-0x2f. First write the address which is 16-bits, followed by the data which is 8-bits.
The first registers 0-127 are used to control the GPIO. Registers 128-255 control the crossbar for the various pins. Use the IO offsets int the second table for the GPIO and CROSSBAR registers.
| Address | Bits | Description |
|---|---|---|
| 127:0 | 7:3 | Reserved (Write 0) |
| 2 | GPIOn Input Data | |
| 1 | GPIOn Output Data | |
| 0 | GPIOn Output Enable | |
| 128:255 | 7 | CROSSBARn GPIO mode |
| 6:0 | CROSSBARn Value | |
| 271:256 | 7:0 | GPIOn Bank Input |
| 287:272 | 7:0 | GPIOn Bank Output Data |
| 288:303 | 7:0 | GPIOn Bank Output Enable (1=out) |
| 304 | 7:0 | Model Number MSB (0x41) |
| 305 | 7:0 | Model Number LSB (0x00) |
| 306 | 7:0 | FPGA Rev |
| 8191:307 | 7:0 | Reserved |
| 16384:8192 | 7:0 | ZPU RAM access |
In the above table the GPIO, Crossbar, and Bank registers will use the following IO. The bank registers should divide the IO number by 8 to get the offset, and use the modulus to get the bit number.
| IO Number | Pad | Crossbar support | Direction |
|---|---|---|---|
| 1 | UART3_TXD_PAD (ttymxc2) | Y | Input |
| 2 | UART3_RTS_PADn (ttymxc2) | Y | Input |
| 3 | UART4_TXD_PAD (ttymxc3) | Y | Input |
| 4 | UART7_TXD_PAD (ttymxc6) | Y | Input |
| 5 | UART_A_RXD_PAD | Y | Input |
| 6 | UART_B_RXD_PAD | Y | Input |
| 7 | UART_C_RXD_PAD | Y | Input |
| 8 | UART_D_RXD_PAD | Y | Input |
| 9 | SPARE_1_PAD | Y | GPIO |
| 10 | SPARE_2_PAD | Y | GPIO |
| 11 | UART_3_RXD_PAD (ttymxc2) | DIO+WIFI | Output |
| 12 | UART_3_CTS_PADN (ttymxc2) | DIO+WIFI | Output |
| 13 | UART4_RXD_PADN (ttymxc3) | DIO+WIFI | Output |
| 14 | UART7_RXD_PAD (ttymxc6) | DIO+WIFI | Output |
| 15 | UART_A_TXD_PAD | DIO+WIFI | Output |
| 16 | UART_B_TXD_PAD | DIO+WIFI | Output |
| 17 | UART_C_TXD_PAD | DIO+WIFI | Output |
| 18 | UART_D_TXD_PAD | DIO+WIFI | Output |
| 19 | WIFI_TXD_PAD | DIO+WIFI | Output |
| 20 | WIFI_CTS_PAD | DIO+WIFI | Output |
| 21 | ZPU_BREAK | N | Input |
| 22 | ZPU_RESET | N | Output |
| 23 | EN_WIFI_PWR_PAD [1] | N | Output |
| 24 | WIFI_RESET_PAD | N | Output |
| 25 | EN_USB_HOST_5V_PAD | N | Output |
| 26 | EN_LCD_3V3_PAD | N | Output |
| 27 | EN_SD_POWER_PAD | N | Output |
| 28 | OFF_BD_RESET_PADN | N | Output |
| 29 | EN_SW_3V3_PADN | N | Output |
| 30 | GREEN_LED_PADN | N | Output |
| 31 | RED_LED_PADN | N | Output |
| 78:32 | DIO_PAD[46:0] | UART+SPARE pins | Output |
| 79 | WIFI_RXD_PAD | Y | Input |
| 80 | WIFI_RTS_PAD | Y | Input |
- ↑ The WIFI driver toggles this automatically. There should be no need to manually control this pin for power savings.