TS-4100 FPGA: Difference between revisions

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|-
|-
| 1
| 1
| UART3_TXD_PAD (ttymxc2)
| SPARE_1_PAD
| Y
| Y
| Input
| GPIO
|-
|-
| 2
| 2
| UART3_RTS_PADn (ttymxc2)
| SPARE_2_PAD
| Y
| Y
| Input
| GPIO
|-
|-
| 3
| 3
| UART4_TXD_PAD (ttymxc3)
| SPARE_3_PAD
| Y
| Y
| Input
| GPIO
|-
|-
| 4
| 4
| UART7_TXD_PAD (ttymxc6)
| SPARE_4_PAD
| Y
| Y
| Input
| GPIO
|-
|-
| 5
| 5
| UART_A_RXD_PAD
| UART3_TXD_PAD (ttymxc2)
| Y
| Y
| Input
| Input
|-
|-
| 6
| 6
| UART_B_RXD_PAD
| UART3_RTS_PADn (ttymxc2)
| Y
| Y
| Input
| Input
|-
|-
| 7
| 7
| UART_C_RXD_PAD
| UART4_TXD_PAD (ttymxc3)
| Y
| Y
| Input
| Input
|-
|-
| 8
| 8
| UART_D_RXD_PAD
| UART7_TXD_PAD (ttymxc6)
| Y
| Y
| Input
| Input
|-
|-
| 9
| 9
| SPARE_1_PAD
| UART_3_RXD_PAD
| Y
| Y
| GPIO
| Output
|-
|-
| 10
| 10
| SPARE_2_PAD
| UART_3_CTS_PAD
| Y
| Y
| GPIO
| Output
|-
|-
| 11
| 11
| UART_3_RXD_PAD (ttymxc2)
| UART4_RXD_PAD
| DIO+WIFI
| Y
| Output
| Output
|-
|-
| 12
| 12
| UART_3_CTS_PADN (ttymxc2)
| UART7_RXD_PAD
| DIO+WIFI
| Y
| Output
| Output
|-
|-
| 13
| 13
| UART4_RXD_PADN (ttymxc3)
| WIFI_RXD_PAD
| DIO+WIFI
| Y
| Output
| Input
|-
|-
| 14
| 14
| UART7_RXD_PAD (ttymxc6)
| WIFI_RTS_PAD
| DIO+WIFI
| Y
| Output
| Input
|-
|-
| 15
| 15
| UART_A_TXD_PAD
| WIFI_IRQ_PADN
| DIO+WIFI
| Y
| Output
| Input
|-
|-
| 16
| 16
| UART_B_TXD_PAD
| WIFI_TXD_PAD
| DIO+WIFI
| Y
| Output
| Output
|-
|-
| 17
| 17
| UART_C_TXD_PAD
| WIFI_CTS_PAD
| DIO+WIFI
| Y
| Output
| Output
|-
|-
| 18
| 18
| UART_D_TXD_PAD
| ZPU_BREAK
| DIO+WIFI
| N
| Output
| Input
|-
|-
| 19
| 19
| WIFI_TXD_PAD
| ZPU_RESET
| DIO+WIFI
| N
| Output
| Output
|-
|-
| 20
| 20
| WIFI_CTS_PAD
| EN_WIFI_PWR_PAD
| DIO+WIFI
| DIO
| Output
| Output
|-
|-
| 21
| 21
| [[#ZPU|ZPU_BREAK]]
| WIFI_RESET_PAD
| N
| DIO
| Input
| Output
|-
|-
| 22
| 22
| [[#ZPU|ZPU_RESET]]
| EN_USB_HOST_5V_PAD
| N
| DIO
| Output
| Output
|-
|-
| 23
| 23
| EN_WIFI_PWR_PAD <ref>The WIFI driver toggles this automatically.  There should be no need to manually control this pin for power savings.</ref>
| EN_LCD_3V3_PAD
| N
| DIO
| Output
| Output
|-
|-
| 24
| 24
| WIFI_RESET_PAD
| EN_SD_POWER_PAD
| N
| DIO
| Output
| Output
|-
|-
| 25
| 25
| EN_USB_HOST_5V_PAD
| OFF_BD_RESET_PADN
| N
| DIO
| Output
| Output
|-
|-
| 26
| 26
| EN_LCD_3V3_PAD
| EN_SW_3V3_PAD
| N
| DIO
| Output
| Output
|-
|-
| 27
| 27
| EN_SD_POWER_PAD
| GREEN_LED_PADN
| N
| DIO
| Output
| Output
|-
|-
| 28
| 28
| OFF_BD_RESET_PADN
| RED_LED_PADN
| N
| DIO
| Output
| Output
|-
|-
| 29
| 29
| EN_SW_3V3_PADN
| UART_A_RXD_PAD
| N
| UART+Spares
| Output
| GPIO
|-
|-
| 30
| 30
| GREEN_LED_PADN
| UART_B_RXD_PAD
| N
| UART+Spares
| Output
| GPIO
|-
|-
| 31
| 31
| RED_LED_PADN
| UART_C_RXD_PAD
| N
| UART+Spares
| Output
| GPIO
|-
| 32
| UART_D_RXD_PAD
| UART+Spares
| GPIO
|-
| 33
| UART_A_TXD_PAD
| UART+Spares
| GPIO
|-
| 34
| UART_B_TXD_PAD
| UART+Spares
| GPIO
|-
| 35
| UART_C_TXD_PAD
| UART+Spares
| GPIO
|-
| 36
| UART_D_TXD_PAD
| UART+Spares
| GPIO
|-
|-
| 78:32
| 83:37
| DIO_PAD[46:0]
| DIO_PADS[46:0]
| UART+SPARE pins
| UART+SPARE pins
| Output
| Output
|-
|-
| 79
| WIFI_RXD_PAD
| Y
| Input
|-
| 80
| WIFI_RTS_PAD
| Y
| Input
|}
|}


<References />
<References />

Revision as of 15:19, 6 June 2016

The TS-4100 FPGA registers are accessed over I2C. The /sys/class/gpio driver provides access to the IO using these registers. See the #GPIO section for more information on the recommended method for IO access.

The FPGA is available at I2C addresses 0x28-0x2f. First write the address which is 16-bits, followed by the data which is 8-bits.

The first registers 0-127 are used to control the GPIO. Registers 128-255 control the crossbar for the various pins. Use the IO offsets int the second table for the GPIO and CROSSBAR registers.

GPIO_n Register
Address Bits Description
127-0 7:3 Reserved (Write 0)
2 GPIOn Input Data
1 GPIOn Output Data
0 GPIOn Output Enable
128-255 7 CROSSBARn GPIO mode
6:0 CROSSBARn Value
271-256 7:0 GPIOn Bank Input
287-272 7:0 GPIOn Bank Output Data
288-303 7:0 GPIOn Bank Output Enable (1=out)
304 7:0 Model Number MSB (0x41)
305 7:0 Model Number LSB (0x00)
306 7:0 FPGA Rev
8191-307 7:0 Reserved
16384-8192 7:0 ZPU RAM access

In the above table the GPIO, Crossbar, and Bank registers will use the following IO. The bank registers should divide the IO number by 8 to get the offset, and use the modulus to get the bit number.

FPGA IO
IO Number Pad Crossbar support Direction
1 SPARE_1_PAD Y GPIO
2 SPARE_2_PAD Y GPIO
3 SPARE_3_PAD Y GPIO
4 SPARE_4_PAD Y GPIO
5 UART3_TXD_PAD (ttymxc2) Y Input
6 UART3_RTS_PADn (ttymxc2) Y Input
7 UART4_TXD_PAD (ttymxc3) Y Input
8 UART7_TXD_PAD (ttymxc6) Y Input
9 UART_3_RXD_PAD Y Output
10 UART_3_CTS_PAD Y Output
11 UART4_RXD_PAD Y Output
12 UART7_RXD_PAD Y Output
13 WIFI_RXD_PAD Y Input
14 WIFI_RTS_PAD Y Input
15 WIFI_IRQ_PADN Y Input
16 WIFI_TXD_PAD Y Output
17 WIFI_CTS_PAD Y Output
18 ZPU_BREAK N Input
19 ZPU_RESET N Output
20 EN_WIFI_PWR_PAD DIO Output
21 WIFI_RESET_PAD DIO Output
22 EN_USB_HOST_5V_PAD DIO Output
23 EN_LCD_3V3_PAD DIO Output
24 EN_SD_POWER_PAD DIO Output
25 OFF_BD_RESET_PADN DIO Output
26 EN_SW_3V3_PAD DIO Output
27 GREEN_LED_PADN DIO Output
28 RED_LED_PADN DIO Output
29 UART_A_RXD_PAD UART+Spares GPIO
30 UART_B_RXD_PAD UART+Spares GPIO
31 UART_C_RXD_PAD UART+Spares GPIO
32 UART_D_RXD_PAD UART+Spares GPIO
33 UART_A_TXD_PAD UART+Spares GPIO
34 UART_B_TXD_PAD UART+Spares GPIO
35 UART_C_TXD_PAD UART+Spares GPIO
36 UART_D_TXD_PAD UART+Spares GPIO
83:37 DIO_PADS[46:0] UART+SPARE pins Output


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