TS-4100 FPGA

The TS-4100 FPGA registers are accessed over I2C. The /sys/class/gpio driver provides access to the IO using these registers. See the GPIO section for more information on the recommended method for IO access.

The FPGA is available at I2C addresses 0x28-0x2F. Accessing the registers requires a chip address write, then a 16-bit register address write, then 8-bit data values.

We provide a simple access mechanism to the FPGA using the 'tshwctl' utility.

The first registers 0-127 are used to control the GPIO. Registers 128-255 control the crossbar for the various pins. Use the IO offsets int the second table for the GPIO and CROSSBAR registers.

GPIO_n Register

Address	Bits	Description
0-127	7:3	Reserved (Write 0)
	2	GPIOn Input Data
	1	GPIOn Output Data
	0	GPIOn Output Enable
128-255	7	CROSSBARn GPIO mode
	6:0	CROSSBARn Value
256-271	7:0	GPIOn Bank Input
272-287	7:0	GPIOn Bank Output Data
288-303	7:0	GPIOn Bank Output Enable (1=out)
304	7:0	Model Number MSB (0x41)
305	7:0	Model Number LSB (0x00)
306	7:0	FPGA Rev
307-8191	7:0	Reserved
8192-16384	7:0	ZPU RAM access

In the above table the GPIO, Crossbar, and Bank registers will use the following IO. The bank registers should divide the IO number by 8 to get the offset, and use the modulus to get the bit number.

FPGA IO

IO Number	Pad	Crossbar support	Direction
1	SPARE_1_PAD	Y	GPIO
2	SPARE_2_PAD	Y	GPIO
3	Reserved	N/A	N/A
4	Reserved	N/A	N/A
5	UART3_TXD_PAD (ttymxc2)	Y	Input
6	UART3_RTS_PADn (ttymxc2)	Y	Input
7	UART4_TXD_PAD (ttymxc3)	Y	Input
8	UART7_TXD_PAD (ttymxc6)	Y	Input
9	UART3_RXD_PAD	Y	Output
10	UART3_CTS_PAD	Y	Output
11	UART4_RXD_PAD	Y	Output
12	UART7_RXD_PAD	Y	Output
13	WIFI_RXD_PAD	Y	Input
14	WIFI_RTS_PAD	Y	Input
15	WIFI_IRQ_PADN	Y	Input
16	WIFI_TXD_PAD	Y	Output
17	WIFI_CTS_PAD	Y	Output
18	ZPU_BREAK	N	Input
19	ZPU_RESET	N	Output
20	EN_WIFI_PWR_PAD	DIO	Output
21	WIFI_RESET_PAD	DIO	Output
22	EN_USB_HOST_5V_PAD	DIO	Output
23	EN_LCD_3V3_PAD	DIO	Output
24	EN_SD_POWER_PAD	DIO	Output
25	OFF_BD_RESET_PADN	DIO	Output
26	EN_SW_3V3_PAD	DIO	Output
27	GREEN_LED_PADN	DIO	Output
28	RED_LED_PADN	DIO	Output
29	UART_A_RXD_PAD	UART+Spares	GPIO
30	UART_B_RXD_PAD	UART+Spares	GPIO
31	UART_C_RXD_PAD	UART+Spares	GPIO
32	UART_D_RXD_PAD	UART+Spares	GPIO
33	UART_A_TXD_PAD	UART+Spares	GPIO
34	UART_B_TXD_PAD	UART+Spares	GPIO
35	UART_C_TXD_PAD	UART+Spares	GPIO
36	UART_D_TXD_PAD	UART+Spares	GPIO
37	DIO_0	UART+SPARE pins	GPIO
38	DIO_1	UART+SPARE pins	GPIO
39	DIO_2	UART+SPARE pins	GPIO
40	DIO_3	UART+SPARE pins	GPIO
41	DIO_4	UART+SPARE pins	GPIO
42	DIO_5	UART+SPARE pins	GPIO
43	DIO_6	UART+SPARE pins	GPIO
44	DIO_7	UART+SPARE pins	GPIO
45	DIO_8	UART+SPARE pins	GPIO
46	DIO_9	UART+SPARE pins	GPIO
47	DIO_10	UART+SPARE pins	GPIO
48	DIO_11	UART+SPARE pins	GPIO
49	DIO_12	UART+SPARE pins	GPIO
50	DIO_13	UART+SPARE pins	GPIO
51	DIO_14	UART+SPARE pins	GPIO
52	DIO_15	UART+SPARE pins	GPIO
53	DIO_16	UART+SPARE pins	GPIO
54	DIO_17	UART+SPARE pins	GPIO
55	DIO_18	UART+SPARE pins	GPIO
56	DIO_19	UART+SPARE pins	GPIO
57	DIO_20	UART+SPARE pins	GPIO
58	DIO_21	UART+SPARE pins	GPIO
59	DIO_22	UART+SPARE pins	GPIO
60	DIO_23	UART+SPARE pins	GPIO
61	DIO_24	UART+SPARE pins	GPIO
62	DIO_25	UART+SPARE pins	GPIO
63	DIO_26	UART+SPARE pins	GPIO
64	DIO_27	UART+SPARE pins	GPIO
65	DIO_28	UART+SPARE pins	GPIO
66	DIO_29	UART+SPARE pins	GPIO
67	DIO_30	UART+SPARE pins	GPIO
68	DIO_31	UART+SPARE pins	GPIO
69	DIO_32	UART+SPARE pins	GPIO
70	DIO_33	UART+SPARE pins	GPIO
71	DIO_34	UART+SPARE pins	GPIO
72	DIO_35	UART+SPARE pins	GPIO
73	DIO_36	UART+SPARE pins	GPIO
74	DIO_37	UART+SPARE pins	GPIO
75	DIO_38	UART+SPARE pins	GPIO
76	DIO_39	UART+SPARE pins	GPIO
77	DIO_40	UART+SPARE pins	GPIO
78	DIO_41	UART+SPARE pins	GPIO
79	DIO_42	UART+SPARE pins	GPIO
80	DIO_43	UART+SPARE pins	GPIO
81	DIO_44	UART+SPARE pins	GPIO
82	DIO_45	UART+SPARE pins	GPIO
83	DIO_46	UART+SPARE pins	GPIO