TS-4100 I2C: Difference between revisions
From embeddedTS Manuals
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The second I2C bus is brought out on [[#TS-SOCKET|CN2_28 (SCL) and CN2_30 (SDA)]]. This bus is shared with the on-board FPGA and runs at 400 kHz by default. | The second I2C bus is brought out on [[#TS-SOCKET|CN2_28 (SCL) and CN2_30 (SDA)]]. This bus is shared with the on-board FPGA and runs at 400 kHz by default. | ||
Revision as of 14:09, 22 October 2021
The i.MX6UL supports standard I2C at 100khz, or using fast mode for 400khz operation. The CPU has 2 I2C buses used on the TS-4100.
I2C 1 is internal to the TS-4100 and only connects to the on-board supervisory microcontroller.
| Address | Device |
|---|---|
| 0x4A | Supervisory Microcontroller |
The second I2C bus is brought out on CN2_28 (SCL) and CN2_30 (SDA). This bus is shared with the on-board FPGA and runs at 400 kHz by default.
| Address | Device |
|---|---|
| 0x28-0x2F | FPGA |
| Note: | It is also possible to request the kernel to use arbitrary GPIO pins as an I2C interface. See an example here. |
The kernel makes the I2C busses available at /dev/i2c-#. The "i2c-tools" (i2cdetect, i2cget, i2cset) package can be used to interact with the bus. Or a specific application can be created.