TS-4100 I2C: Difference between revisions
From embeddedTS Manuals
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The i.MX6UL supports standard I2C at 100khz, or using fast mode for 400khz operation. The CPU has 2 I2C buses used on the TS-4100. | The i.MX6UL supports standard I2C at 100khz, or using fast mode for 400khz operation. The CPU has 2 I2C buses used on the TS-4100. | ||
I2C 1 is internal to the TS-4100 and connects | I2C 1 is internal to the TS-4100 and only connects to the on-board supervisory microcontroller. | ||
{| class=wikitable | {| class=wikitable | ||
|+ /dev/i2c-0 | |+ /dev/i2c-0 | ||
| Line 8: | Line 8: | ||
! Device | ! Device | ||
|- | |- | ||
| | | 0x4A | ||
| [[# | | [[#Supervisory_Microcontroller|Supervisory Microcontroller]] | ||
|} | |} | ||
The second I2C bus is brought out on CN2_28 (SCL) and CN2_30 (SDA). | |||
The second I2C bus is brought out on [[#TS-SOCKET|CN2_28 (SCL) and CN2_30 (SDA)]]. This bus is shared with the on-board FPGA and runs at 400 kHz by default. | |||
{| class=wikitable | {| class=wikitable | ||
|+ /dev/i2c-2 | |+ /dev/i2c-2 | ||
| Line 19: | Line 20: | ||
! Device | ! Device | ||
|- | |- | ||
| 0x28- | | 0x28-0x2F | ||
| [[#FPGA]] | | [[#FPGA|FPGA]] | ||
|} | |} | ||
{{Note|It is also possible to request the kernel to | {{Note|It is also possible to request the kernel to use arbitrary GPIO pins as an I2C interface. See an example [https://github.com/embeddedTS/linux-3.10.17-imx6/blob/619e6bf97479243e9d7b7f6b34ce0ae8558ff1fd/arch/arm/boot/dts/imx6qdl-ts4900-2.dtsi#L196 here].}} | ||
The kernel makes the I2C available at /dev/i2c-#. | The kernel makes the I2C busses available at /dev/i2c-#. The "i2c-tools" (i2cdetect, i2cget, i2cset) package can be used to interact with the bus. Or a specific [https://github.com/embeddedTS/linux-4.9.y/tree/master/Documentation/i2c/dev-interface application can be created]. | ||
Latest revision as of 16:42, 17 January 2022
The i.MX6UL supports standard I2C at 100khz, or using fast mode for 400khz operation. The CPU has 2 I2C buses used on the TS-4100.
I2C 1 is internal to the TS-4100 and only connects to the on-board supervisory microcontroller.
| Address | Device |
|---|---|
| 0x4A | Supervisory Microcontroller |
The second I2C bus is brought out on CN2_28 (SCL) and CN2_30 (SDA). This bus is shared with the on-board FPGA and runs at 400 kHz by default.
| Address | Device |
|---|---|
| 0x28-0x2F | FPGA |
| Note: | It is also possible to request the kernel to use arbitrary GPIO pins as an I2C interface. See an example here. |
The kernel makes the I2C busses available at /dev/i2c-#. The "i2c-tools" (i2cdetect, i2cget, i2cset) package can be used to interact with the bus. Or a specific application can be created.