TS-4100 I2C: Difference between revisions
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The second I2C bus is brought out on CN2_28 (SCL) and CN2_30 (SDA). This is shared with the onboard FPGA and it goes offboard. This bus also runs at 400khz by default. | The second I2C bus is brought out on CN2_28 (SCL) and CN2_30 (SDA). This is shared with the onboard FPGA and it goes offboard. This bus also runs at 400khz by default. | ||
{| class=wikitable | {| class=wikitable | ||
|+ /dev/i2c- | |+ /dev/i2c-2 | ||
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! Address | ! Address |
Revision as of 16:11, 8 June 2016
The i.MX6 supports standard I2C at 100khz, or using fast mode for 400khz operation. The CPU has 2 I2C buses used on the TS-4100.
I2C 1 is internal to the TS-4100 and connects just to the onboard Silabs supervisory microcontroller at 100khz.
Address | Device |
---|---|
0x10 | #Silabs |
The second I2C bus is brought out on CN2_28 (SCL) and CN2_30 (SDA). This is shared with the onboard FPGA and it goes offboard. This bus also runs at 400khz by default.
Address | Device |
---|---|
0x28-0x2f | #FPGA |
Note: | It is also possible to request the kernel to bitbang additional I2C buses as needed. See an example here. |
The kernel makes the I2C available at /dev/i2c-#. You can use the i2c-tools (i2cdetect, i2cget, i2cset), or you can write your own client.