TS-4500
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Cavium CNS2132 Datasheet |
UNDER CONSTRUCTION
PC104
To enable PC104 on the TS-4500 with a TS8160 baseboard, a timing register on the FPGA must be set.
To do this, use this command:
sbuspoke 0x20000 0x181
This will set the bus timing to enabled, with an extra CS pulse time of 3 clock cycles.
Code Sample
This code sample demonstrates how to implement the use of the TS-RLY8 on the PC104 bus.
#include "sbus.h"
#include <stdio.h>
// The fist two defines are specific to the TS-4500.
#define TS4500_TIMING_REGISTER 0x20000
#define TIMING_VALUE 0x181
// The TS-RLY8 base address is jumper-selectable.
// The one used in testing this code was at 0x140.
#define RLY_BASEADDR 0x140
int main(void)
{
int i = 0; // loop variable
unsigned short pc104ID = 0;
int timing = 0;
// The sbus must be locked before transactions can take place.
sbuslock();
// Set timing for the PC104 bus.
timing = winpeek16(TS4500_TIMING_REGISTER);
winpoke16(TS4500_TIMING_REGISTER, TIMING_VALUE);
// Get the ID of the card at the base address.
// For the TS-RLY8 this should return 0x9b
pc104ID = winpeek8(RLY_BASEADDR);
// Loop through all possible position combinations on the TS-RLY8
for(i = 0; i < 255; i++)
{
winpoke16(RLY_BASEADDR+2,i); // Relay address space starts at base + 2.
// Avoid holding the sbus for too long by using preempt.
sbuspreempt();
usleep(20000);
}
// Return the timing register to what it was before.
winpoke16(TS4500_TIMING_REGISTER, timing);
sbusunlock();
// Output the result of the board ID check.
if(pc104ID > 0)
printf("0x%x returned from sbus_peek8(0x%x)\n",pc104ID, RLY_BASEADDR);
return 0;
}