TS-47XX DIO: Difference between revisions
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Revision as of 14:51, 15 October 2013
This board uses both CPU and a DIO controller in the FPGA. The CPU DIO typically has 1-7 functions associated with various pins (I2C, PWM, SPI, etc). See the CPU manual CPU manual for the complete listing and for information on how to control these DIO. For purposes of identity, all FPGA DIO will be labelled DIO_n (where n is the DIO pin number), and all CPU dio will be labelled MFP_n.
Bit masking: Any bits not expressly mentioned here should be masked out. Direction setting: 0 is input, 1 is output.
All FPGA DIO are controlled by three distinct register types: Direction, Input Data, and Output Data. To use any DIO pin, the direction register must be set (0 for input, 1 for output), then either the input register may be read, or the output register may be written to. These registers are described in the Syscon memory table.
For example, to write to DIO_0, bit 0 (the LSB) of 0x80004018 (The direction register for DIO_0 through DIO_14) must be set high, then the desired value (high = 1 low = 0) should be written to bit 0 of 0x80004010 (the Output Data register for DIO_0 through DIO_14). Alternatively to read the status of that pin, the Direction Register must be set low, then bit zero of 0x80004020 would reflect the status of that pin.
Full details on CPU pins can be found in the CPU manual, along with mode and mapping assignments specific to the CPU. As this comprises twelve pages of material that must be completely understood, it is best to read the CPU manual carefully before making use of these pins.
The pages of interest in the CPU manual regarding the MFP_n pins start at page A-5 and continue through page A-12 under section A.1.
General information for DIO access is given here for convenience: CPU GPIO Register base: 0xD4019000 The offsets table for the CPU GPIO pins is on pages A-7 through A-9. The register description for each pin's register is located on pages A-9 through A-12.
All 60 of the DIO from the FPGA will default to the DIO mode. These pins coming from the FPGA are all 3.3V tolerant. To manipulate these DIO you can access the #Syscon.
For simple operations you can use tshwctl to set the FPGA DIO pins:
# Set DIO 30 as a high output
tshwctl --setdio 30
# Set DIO 30 as a low output
tshwctl --clrdio 30
# Read the input value of DIO 42, 43, 44
# This will set the pin to an input and return the value
tshwctl --getdio 42,43,44