The FPGA includes a core for communicating with the MCP3428 ADC controller we use on several of our baseboards. If you are using this on your own baseboard this core assumes the standard circuit which allows 2 differential channels and 4 single-ended channels. The single-ended channels are chosen using analog muxes controlled by the AN_SEL line. Since different baseboards use a different pin for AN_SEL, a register is also provided to select the correct lines.
Channels 1 and 2 are differential channels with a range of -2.048V to +2.048V. Channels 3-6 are 0 to 10.24V.
The channel mask register controls which channels are enabled. Bits 0-5 enable channels 1-6 respectively. If a given channel is not enabled, (enable bit == 0) it will not be sampled and its conversion value register will contain an obsolete and meaningless value. The more channels that are enabled, the lower the sampling speed on each channel.
| Offset
|
Bits
|
Description
|
| 0x0
|
15:8
|
Core ID register (reads 0xad)
|
| 7:6
|
Reserved
|
| 5:4
|
Analog Select Pin
| Value
|
Description
|
| 0
|
Do not use an AN+SEL
|
| 1
|
use CN1 pin 77 for AN_SEL (TS-8100)
|
| 2
|
use CN1 pin 74 for AN_SEL (TS-8390)
|
| 3
|
Reserved
|
|
| 3:2
|
Speed
| Value
|
Description
|
| 0
|
240Hz, 12 bit resolution
|
| 1
|
60Hz, 14 bit resolution
|
| 2
|
15Hz, 16 bit resolution
|
| 3
|
Reserved
|
|
| 1:0
|
Programmable Gain Amplifier
| Value
|
Description
|
| 0
|
No gain
|
| 1
|
2x gain
|
| 2
|
4x gain
|
| 3
|
8x gain
|
|
| 0x2
|
15:0
|
Channel Mask
|
| 0x4
|
15:0
|
Channel 1 most recent conversion value
|
| 0x6
|
15:0
|
Channel 2 most recent conversion value
|
| 0x8
|
15:0
|
Channel 3 most recent conversion value
|
| 0xa
|
15:0
|
Channel 4 most recent conversion value
|
| 0xc
|
15:0
|
Channel 5 most recent conversion value
|
| 0xe
|
15:0
|
Channel 6 most recent conversion value
|
