TS-4900 COM Ports: Difference between revisions

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The FPGA also includes 3 additional SPI UARTs very similar to the MAX3100 UART.  It is possible to use the standard max3100 driver with the FPGA uarts, but only one UART will be accessible.  The FPGA includes a difference from the MAX3100 chipset in that a byte should precede other SPI traffic to select which "max3100" core is being addressed.  The MAX3100s also include an FPGA change to route out a transmit enable for automatic RS485 half duplex direction control.
The FPGA also includes 3 additional SPI UARTs very similar to the MAX3100 UART.  It is possible to use the standard max3100 driver with the FPGA uarts, but only one UART will be accessible.  The FPGA includes a difference from the MAX3100 chipset in that a byte should precede other SPI traffic to select which "max3100" core is being addressed.  The MAX3100s also include an FPGA change to route out a transmit enable for automatic RS485 half duplex direction control.


All of these UARTs are accessed using the standard /dev/ interfaces.  See these resources for information on programming with UARTs in Linux.
{{:Standard UART Examples}}
 
*[http://en.wikibooks.org/wiki/Serial_Programming/Serial_Linux Wikibook]
*[http://tldp.org/HOWTO/Serial-Programming-HOWTO/index.html Linux Documentation Project Serial Programming Guide]

Revision as of 10:32, 20 July 2016

This board uses UARTs from both the CPU and the FPGA. The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be repurposed. The other CPU uarts for ttymxc1-4 are usable for end applications. These support up to 5Mb/s UART data, and are routed through the onboard FPGA to provide automatic direction control for half duplex RS-485 with tshwctl.

The FPGA also includes 3 additional SPI UARTs very similar to the MAX3100 UART. It is possible to use the standard max3100 driver with the FPGA uarts, but only one UART will be accessible. The FPGA includes a difference from the MAX3100 chipset in that a byte should precede other SPI traffic to select which "max3100" core is being addressed. The MAX3100s also include an FPGA change to route out a transmit enable for automatic RS485 half duplex direction control.

All of these UARTs are accessed using the standard /dev/ interfaces. See these resources for information on programming with UARTs in Linux.