TS-4900 COM Ports

This board uses UARTs from both the CPU and the FPGA. The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be repurposed. The other CPU uarts for ttymxc1-4 are usable for end applications. These support up to 5Mb/s UART data, and are routed through the onboard FPGA to provide automatic direction control for half duplex RS-485 with tshwctl.

The FPGA also includes 3 additional SPI UARTs very similar to the MAX3100 UART. It is possible to use the standard max3100 driver with the FPGA uarts, but only one UART will be accessible. The FPGA includes a difference from the MAX3100 chipset in that a byte should precede other SPI traffic to select which "max3100" core is being addressed. The MAX3100s also include an FPGA change to route out a transmit enable for automatic RS485 half duplex direction control.

None of the RS232/TTL ports require special setup, but the RS485 ttymxc3, or ttymxc1 if used for 485 requires some set up. RS485 half duplex requires toggling a pin to switch between transmit and receive. The ttyMAX uarts include this as part of the FPGA hardware so no setup is required for these, but the CPU UARTs do not do this automatically. The CPU UARTs instead are passed through the FPGA which can generate an automatic transmit enable signal by knowing the bit rate and symbol size.

For example:

root@ts-imx6:~# stty -F /dev/ttymxc3  115200
root@ts-imx6:~# stty -F /dev/ttymxc3 
speed 115200 baud; line = 0;
-brkint -imaxbel
root@ts-imx6:~# tshwctl --autotxen 3
Setting Auto TXEN for 115200 baud and 10 bits per symbol from current settings

tshwctl will read the uart settings currently applied when it is run and it sets up the FPGA's timing for TXEN when it is run. Your baud rate and mode settings should be set before running this.

For 8n1, this will include 8 data bits, no parity, 1 stop bit, as well as one start bit adding up to 10 bits per symbol. 9n1 or parity modes may have more or less bits per symbol.

The ttyMAX ports will work for most situations, but these ports have a couple limitations. It can support about two 115200 links saturated with data, but not a third. This limitation does not apply to the uart being open, but only when there is data actively being transmitted. The FPGA crossbar allows you to change which uarts are mapped where, so you can adjust which uarts are low bandwidth.

All of these UARTs are accessed using the standard /dev/ interfaces. See these resources for information on programming with UARTs in Linux.

• Wikibook
• Linux Documentation Project Serial Programming Guide