TS-4900 COM Ports: Difference between revisions
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This board uses UARTs from both the CPU and the FPGA. The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be repurposed. The other CPU | This board uses UARTs from both the CPU and the FPGA. The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be repurposed. The other CPU UARTs for ttymxc1-4 are usable for end applications. These support up to 5Mb/s UART data. The CPU UARTs are routed through the onboard FPGA. This allows these UARTs to support direction control for RS-485 with tshwctl. | ||
The FPGA also includes 3 | The FPGA also includes 3 extra SPI UARTs like the MAX3100 UART. It is possible to use the standard max3100 driver with the FPGA UARTs, but only one UART will be accessible. The FPGA includes one significant difference from the MAX3100 chipset. A byte should precede other SPI traffic to select which "max3100" core is being addressed. The MAX3100s also support transmit enable for automatic RS485 half duplex direction control. | ||
None of the RS232/TTL ports | None of the RS232/TTL ports need special setup, but the RS485 ttymxc3, or ttymxc1 if used for 485 requires some set up. RS485 half duplex requires toggling a pin to switch between transmit and receive. The ttyMAX uarts include this as part of the FPGA hardware so no setup is required. The CPU UARTs do not do this automatically. The CPU's UARTs are passed through the FPGA to create an automatic transmit enable. This requires the FPGA to know the bit rate and symbol size. | ||
For example: | For example: | ||
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</pre> | </pre> | ||
tshwctl will read the | The tshwctl tool will read the UART settings when it is run and it sets up the FPGA's timing for TXEN. Your baud rate and mode settings should be set before running this. | ||
For 8n1, this will include 8 data bits, no parity, 1 stop bit, as well as one start bit adding up to 10 bits per symbol. 9n1 or parity modes may have more or less bits per symbol. | For 8n1, this will include 8 data bits, no parity, 1 stop bit, as well as one start bit adding up to 10 bits per symbol. 9n1 or parity modes may have more or less bits per symbol. | ||
The ttyMAX ports will work for most situations, but these ports have a couple limitations. It can support about two 115200 links saturated with data, but not a third. This limitation | The ttyMAX ports will work for most situations, but these ports have a couple limitations. It can support about two 115200 links saturated with data, but not a third. This limitation only applies when data is actively being transmitted, not idle UARTs. The FPGA crossbar allows changing UART mappings so bandwidth can be prioritized. | ||
{{:Standard UART Examples}} | {{:Standard UART Examples}} | ||
Revision as of 17:52, 10 February 2017
This board uses UARTs from both the CPU and the FPGA. The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be repurposed. The other CPU UARTs for ttymxc1-4 are usable for end applications. These support up to 5Mb/s UART data. The CPU UARTs are routed through the onboard FPGA. This allows these UARTs to support direction control for RS-485 with tshwctl.
The FPGA also includes 3 extra SPI UARTs like the MAX3100 UART. It is possible to use the standard max3100 driver with the FPGA UARTs, but only one UART will be accessible. The FPGA includes one significant difference from the MAX3100 chipset. A byte should precede other SPI traffic to select which "max3100" core is being addressed. The MAX3100s also support transmit enable for automatic RS485 half duplex direction control.
None of the RS232/TTL ports need special setup, but the RS485 ttymxc3, or ttymxc1 if used for 485 requires some set up. RS485 half duplex requires toggling a pin to switch between transmit and receive. The ttyMAX uarts include this as part of the FPGA hardware so no setup is required. The CPU UARTs do not do this automatically. The CPU's UARTs are passed through the FPGA to create an automatic transmit enable. This requires the FPGA to know the bit rate and symbol size.
For example:
root@ts-imx6:~# stty -F /dev/ttymxc3 115200 root@ts-imx6:~# stty -F /dev/ttymxc3 speed 115200 baud; line = 0; -brkint -imaxbel root@ts-imx6:~# tshwctl --autotxen 3 Setting Auto TXEN for 115200 baud and 10 bits per symbol from current settings
The tshwctl tool will read the UART settings when it is run and it sets up the FPGA's timing for TXEN. Your baud rate and mode settings should be set before running this.
For 8n1, this will include 8 data bits, no parity, 1 stop bit, as well as one start bit adding up to 10 bits per symbol. 9n1 or parity modes may have more or less bits per symbol.
The ttyMAX ports will work for most situations, but these ports have a couple limitations. It can support about two 115200 links saturated with data, but not a third. This limitation only applies when data is actively being transmitted, not idle UARTs. The FPGA crossbar allows changing UART mappings so bandwidth can be prioritized.
All of these UARTs are accessed using the standard /dev/ interfaces. See these resources for information on programming with UARTs in Linux.