TS-4900 COM Ports: Difference between revisions
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This board uses UARTs from both the CPU and the FPGA. The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be reused. The other CPU UARTs for ttymxc1-4 are usable for end applications. These support up to 5Mb/s UART data with DMA. | This board uses UARTs from both the CPU and the FPGA. The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be reused. The other CPU UARTs for ttymxc1-4 are usable for end applications. These support up to 5Mb/s UART data with DMA. | ||
The FPGA also emulates a MAX3100 UART interface accessible at /dev/ttyMAX0-2. These UARTs support a total throughput of about 115200<ref>Idle periods do not count towards the total throughput limitation.</ref> | The FPGA also emulates a MAX3100 UART interface accessible at /dev/ttyMAX0-2. These UARTs support a total throughput of about 115200<ref>Idle periods do not count towards the total throughput limitation.</ref>. These UARTs include hardware that makes implementing RS-485 half duplex software very simple. If higher throughput is needed, the [[#FPGA_Crossbar|FPGA crossbar]] can be adjusted to use a CPU UART with TXEN support instead. | ||
{{Note|Our SPI interface matches the max3100 almost entirely, except optionally a single 8-bit transaction can be sent to act as a chip select between the three uarts supported on our interface. The default FPGA supports 3 UARTs on this interface. This is handled automatically by our driver (max3100-ts).}} | {{Note|Our SPI interface matches the max3100 almost entirely, except optionally a single 8-bit transaction can be sent to act as a chip select between the three uarts supported on our interface. The default FPGA supports 3 UARTs on this interface. This is handled automatically by our driver (max3100-ts).}} | ||
Revision as of 11:06, 1 August 2017
This board uses UARTs from both the CPU and the FPGA. The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be reused. The other CPU UARTs for ttymxc1-4 are usable for end applications. These support up to 5Mb/s UART data with DMA.
The FPGA also emulates a MAX3100 UART interface accessible at /dev/ttyMAX0-2. These UARTs support a total throughput of about 115200[1]. These UARTs include hardware that makes implementing RS-485 half duplex software very simple. If higher throughput is needed, the FPGA crossbar can be adjusted to use a CPU UART with TXEN support instead.
| Note: | Our SPI interface matches the max3100 almost entirely, except optionally a single 8-bit transaction can be sent to act as a chip select between the three uarts supported on our interface. The default FPGA supports 3 UARTs on this interface. This is handled automatically by our driver (max3100-ts). |
RS-485 half duplex's direction control is built into the ttyMAX UARTs. By default they are connected to the RS-485 ports and no code is required for the transmit enable to toggle. The CPU UARTs however do not have transmit enable built in. The FPGA however includes a core that will toggle transmit enable for ttymxc1/ttymxc3, but it needs to know the baud rate, and symbol size (data bits, parity, stop bits).
For example:
# Configure mxc1 and mxc3 as 115200, 8n1
stty -F /dev/ttymxc1 115200 cs8 -cstopb
tshwctl --autotxen 1
stty -F /dev/ttymxc3 115200 cs8 -cstopb
tshwctl --autotxen 3
The tshwctl tool will read the UART settings from the moment when it is run and it sets up the FPGA's timing for TXEN. Your baud rate and mode settings should be set before running this.
Using the FPGA for either the ttyMAX uarts, or the CPU uarts, the TXEN timing will happen well under a single bit time [2] of any baud rate possible by the hardware.
All of these UARTs are accessed using the standard /dev/ interfaces. See these resources for information on programming with UARTs in Linux.