TS-4900 COM Ports: Difference between revisions

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The TS-4900 uses UARTs from both the CPU and the FPGA.  The CPU uart 0 (/dev/ttymxc0) is dedicated to console for Linux and U-boot and not suggested to be repurposed.  The other CPU uarts for ttymxc1-4 are usable for end applications.  These support up to 5Mb/s UART data, and are routed through the onboard FPGA to provide automatic direction control for half duplex RS-485 with tshwctl.
This board uses UARTs from both the CPU and the FPGA.  The CPU UART 0 (/dev/ttymxc0) is a dedicated console for Linux and U-Boot and not suggested to be reused.  The other CPU UARTs for ttymxc1 through ttymxc4 are usable for end applications.  These support up to 5Mb/s UART data with DMA.


The FPGA also includes 3 additional SPI UARTs very similar to the MAX3100 UART.  It is possible to use the standard max3100 driver with the FPGA uarts, but only one UART will be accessible.  The FPGA includes a difference from the MAX3100 chipset in that a byte should precede other SPI traffic to select which "max3100" core is being addressed.  The MAX3100s also include an FPGA change to route out a transmit enable for automatic RS485 half duplex direction control.
The FPGA also emulates a MAX3100 UART interface accessible at /dev/ttyMAX0-2.  These UARTs support a total throughput of about 115200<ref>Idle periods do not count towards the total throughput limitation.</ref>.  These UARTs include hardware that makes implementing RS-485 half duplex software extremely simple.  If higher throughput is needed, the [[#FPGA_Crossbar|FPGA crossbar]] can be adjusted to use a CPU UART with TXEN support instead.


All of these UARTs are accessed using the standard /dev/ interfaces.  See these resources for information on programming with UARTs in Linux.
{{Note|Our SPI interface matches the max3100 almost entirely, except optionally a single 8-bit transaction can be sent to act as a chip select between the three uarts supported on our interface.  The default FPGA supports 3 UARTs on this interface.  This is handled automatically by our driver (max3100-ts).}}


*[http://en.wikibooks.org/wiki/Serial_Programming/Serial_Linux Wikibook]
The RS-485 half duplex direction control is built into the ttyMAX UARTs.  By default, they are connected to the RS-485 ports and no code is required for the transmit enable to toggle. The CPU UARTs however do not have transmit enable built in. The FPGA provides support for transmit enable on ttymxc1/ttymxc3, but additional setup steps are required so the FPGA can properly time the transmit enable output. The FPGA needs to know the baud rate, and symbol size (data bits, parity, stop bits) that the UART will be run at
*[http://tldp.org/HOWTO/Serial-Programming-HOWTO/index.html Linux Documentation Project Serial Programming Guide]
 
For example:
<source lang=bash>
# Configure ttymxc1 and ttymxc3 as 115200, 8n1
 
stty -F /dev/ttymxc1 115200 cs8 -cstopb
tshwctl --autotxen 1
 
stty -F /dev/ttymxc3 115200 cs8 -cstopb
tshwctl --autotxen 3
</source>
 
The 'tshwctl' tool will read the UART settings and set up the FPGA timing for TXEN automatically. The baud rate and mode settings must be set before running the 'tshwctl' command!
 
When using the FPGA for either the ttyMAX UARTs or the CPU UARTs, the TXEN timing will happen well under a single bit time <ref>This is a requirement for half duplex MODBUS</ref> of any baud rate possible by the hardware.
 
{{:Standard UART Examples}}
 
<References />

Latest revision as of 18:02, 28 September 2018

This board uses UARTs from both the CPU and the FPGA. The CPU UART 0 (/dev/ttymxc0) is a dedicated console for Linux and U-Boot and not suggested to be reused. The other CPU UARTs for ttymxc1 through ttymxc4 are usable for end applications. These support up to 5Mb/s UART data with DMA.

The FPGA also emulates a MAX3100 UART interface accessible at /dev/ttyMAX0-2. These UARTs support a total throughput of about 115200[1]. These UARTs include hardware that makes implementing RS-485 half duplex software extremely simple. If higher throughput is needed, the FPGA crossbar can be adjusted to use a CPU UART with TXEN support instead.

Note: Our SPI interface matches the max3100 almost entirely, except optionally a single 8-bit transaction can be sent to act as a chip select between the three uarts supported on our interface. The default FPGA supports 3 UARTs on this interface. This is handled automatically by our driver (max3100-ts).

The RS-485 half duplex direction control is built into the ttyMAX UARTs. By default, they are connected to the RS-485 ports and no code is required for the transmit enable to toggle. The CPU UARTs however do not have transmit enable built in. The FPGA provides support for transmit enable on ttymxc1/ttymxc3, but additional setup steps are required so the FPGA can properly time the transmit enable output. The FPGA needs to know the baud rate, and symbol size (data bits, parity, stop bits) that the UART will be run at

For example: 

# Configure ttymxc1 and ttymxc3 as 115200, 8n1

stty -F /dev/ttymxc1 115200 cs8 -cstopb
tshwctl --autotxen 1

stty -F /dev/ttymxc3 115200 cs8 -cstopb
tshwctl --autotxen 3

The 'tshwctl' tool will read the UART settings and set up the FPGA timing for TXEN automatically. The baud rate and mode settings must be set before running the 'tshwctl' command!

When using the FPGA for either the ttyMAX UARTs or the CPU UARTs, the TXEN timing will happen well under a single bit time [2] of any baud rate possible by the hardware.

All of these UARTs are accessed using the standard /dev/ interfaces. See these resources for information on programming with UARTs in Linux.

  1. ↑ Idle periods do not count towards the total throughput limitation.
  2. ↑ This is a requirement for half duplex MODBUS
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