TS-5500

TS-5500

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Introduction

The model TS-5500 is a compact, full-featured PC compatible Single Board Computer based on the AMD Elan520 processor. At 133 MHz, it is approximately 10 times faster than our other 386EX based products for only a small additional cost. PC compatibility allows for rapid development since you can use standard PC development tools such as Turbo C or Power Basic or Linux based tools as well. If you have done work in the PC world in the past, you will find you can now build applications for a very small target that does not require a keyboard, video, floppy disks, or hard drives.

By adding the optional TS-9500 daughter board, you can compile and debug directly on the TS-5500 with standard VGA video and keyboard interfaces. Alternatively, you can typically write and debug code on a host PC using standard development tools for the PC platform, then simply copy it to and run it on the TS-5500 without modification. If additional peripherals are required, the PC/104 expansion bus allows for many standard functions available off-the-shelf. It is also very simple to create a custom PC/104 daughter board for those special features that differentiate your product. Technologic Systems can provide technical support as well as a free quotation for any custom hardware, software, or BIOS modifications you may require.

This manual is fairly short. This is because for the most part, the TS-5500 is a standard x86-based PC compatible computer, and there are hundreds of books about writing software for the PC platform. The primary purpose of this manual is documenting where the TS-5500 differs from a standard PC.

PC Compatibility

PC compatibility requires much more than just an x86 processor. It requires PC compatible memory and I/O maps as well as a PC compatible BIOS. The General Software EMBEDDED BIOS offers a high degree of compatibility with past and present BIOS standards allowing it to run off-the shelf operating systems and application software.

The EMBEDDED BIOS has been tested with all major versions of DOS, including MS-DOS, DR-DOS, and Embedded DOS 6-XL; all major versions of OS/2, including MS-OS/2 and IBM OS/2; MS-Windows 3.1, Windows-95, Windows NT, and NetWare 386.

Operating Systems

Technologic Systems Embedded PCs are compatible with a wide variety of x86-based operating systems. A partial list OSes currently used with our boards by customers includes:

• TNT Embedded Toolsuite, Phar Lap Software
• UCos II
• RTKernel, On Time Software
• RTEMS, On-Line Applications Research Corporation
• DOS with WATTCP, public domain TCP/IP source code for DOS
• Linux

The TS-5500 is shipped, free of charge, with Embedded DOS ROM by General Software.

The TS-5500 can be shipped upon request with Linux pre-installed for a nominal fee. The Linux file system and kernel is also freely available on the web should you wish to install it yourself. Typically, the Linux OS requires a 32MB or larger Compact Flash or an M-System�s DiskOnChip.

Power

The TS-5500 requires regulated 5VDC at 900 mA (typical). A quick release screw-down terminal block for the 5V power and power GND connections is provided for easy connection to an external power supply.

When power is first supplied to the TS-5500, the board mounted LED is immediately turned on under hardware control. Once the processor begins execution, the LED is turned off. The LED then turns on then off to provide a characteristic blink during execution of POST. If the LED does not turn on at all, the most likely problem is the power supply. Check that the +5V and GND connections are not reversed. A diode protects the board against damage in such a situation, but it will not run.

Please note that supply voltages over 6 VDC may damage the TS-5500.

Be sure to use a regulated 5 VDC power supply.

Memory

SDRAM

The TS-5500 has a total of 32 Megabytes (MB) of high-speed SDRAM providing 640 Kilobytes (KB) of base memory, 15 MB of extended memory, and 128 KB of shadow RAM for the BIOS. This is identical to a standard PC memory map. The TS-5500 can be ordered with 16MB or 64MB of SDRAM, but it is not field upgradeable.

The TS-5500 SDRAM chips are soldered directly to the board. By not using a SIMM socket, the TS- 5500 is much more reliable in high-vibration environments.

Flash

There is a total of 2 MB of Flash memory on the TS-5500 with 128 KB reserved for the BIOS. During POST, this 128 KB area is copied from Flash into SDRAM at addresses E0000h through FFFFFh for improved performance (a standard technique known as BIOS Shadowing). The remainder of the Flash memory (1920 KB) is configured as two solid-state disk (SSD) drives appearing as drive A and drive B. Drive A uses 896 KB of Flash memory while drive B uses the remaining 1024 KB of Flash memory. Both drives are fully supported by the BIOS as INT 13h drives.

The physical Flash memory is accessed by the BIOS in protected mode at memory address 148M. The Flash memory is guaranteed capable of a minimum of 100,000 write/erase cycles. This means that if you completely erase and rewrite the SSD drive 10 times a day you have over 27 years before any problems would occur. Reading the SSD produces no wear at all.

Power failure during flash writes can cause corruption of flash drive FAT tables (A: or B:). Therefore applications writing frequently should use DiskOnChip or Compact Flash card drives which are more tolerant of power failure during write cycles.

Flash drive A is read-only when JP3 is not installed. Removing JP3 also makes the 128 kbyte BIOS area of the Flash write protected as well. Write protecting the A: drive can be useful if there are critical files in the final product that must be very secure.

Compact Flash cards and DiskOnChip modules

If 2MB of Flash is insufficient for your application, additional non-volatile storage can be added with a Compact Flash card or an M-Systems DiskOnChip module. Either of these products can supply additional storage that will behave much as a hard drive does in a typical PC with sizes ranging from 8MB to 512MB. These products are inherently more rugged than a hard drive since they are completely solid-state with no moving parts.

The Compact Flash card has the added advantage of being removable media. A SanDisk USB Compact Flash reader/writer (which is included in the TS-5500 Developer�s Kit) is recommended for the host PC for file transfers. This results in the ability to quickly move files from a host PC to the TS-5500 using a Compact Flash card as the removable media. Since the Compact Flash card appears as a standard IDE drive on the TS-5500, it uses no additional RAM for drivers. While a USB Compact Flash reader allows for hot swapping of the Compact Flash card on the host PC, the Compact Flash interface on the TS-5500 is not hot swappable, the TS-5500 must be rebooted after removing or installing a Compact Flash card.

The DiskOnChip module can be installed into the 32-pin socket near the center of the board. DiskOnChip modules are available from Technologic Systems as well as other distributors. It is compatible with DOS as shipped, and drivers for other operating systems (such as Linux) are available.

If a DiskOnChip is installed, it will simply appear as drive C. The DiskOnChip is accessed through an 8 KB range of memory at D0000h through D1FFFh. If you are installing a PC/104 daughter card that uses memory mapped I/O, it must not conflict with this address range if the DiskOnChip is installed. Additionally, in a DOS environment the DiskOnChip firmware uses approximately 30 KB of user RAM (below 640 KB).

Using the SanDisk USB Compact Flash Card Reader

This device allows for a very fast and reliable method of moving files between the host PC and target SBC (TS-5500). The Compact Flash (CF) card can then be hot swapped (inserted or removed without rebooting the host PC). Sometimes it is necessary to unplug the USB cable and reinstall it after swapping CF cards (at least Windows ME seems to prefer this).

Note:

The TS-5500 always needs to be powered off before swapping CF cards.

Non-Volatile SRAM

The 32-pin socket can also optionally hold 32 KB of Non-volatile SRAM memory. This behaves exactly like battery-backed SRAM. This or the DiskOnChip may be installed, but not both. Non-volatile SRAM provides non-volatile memory with unlimited write cycles and no write time degradation, unlike Flash memory. The SRAM uses an additional 32 KB range of D0000h through D7FFFh. If the SRAM is installed, PC/104 daughter card that uses memory mapped I/O must not conflict with this address range.

I/O location 75h, bit 0 can be read to determine whether the SRAM option is installed; a �1� in bit 0 indicates that it is installed, a �0� that it is not.

Serial Ports

The three PC compatible asynchronous serial ports (COM1, COM2 and COM3) provide a means to communicate with external serial devices such as printers, modems, etc. Each is independently configured as a standard PC COM port that is compatible with the National Semiconductor NS16C450. Alternatively, these ports can be changed to the 16C550 mode with 16 byte FIFOs in both the receive and transmit UART channels. COM1 appears in the I/O space at 3F8h � 3FFh and uses IRQ4. COM2 is located at 2F8h � 2FFh and uses IRQ3. COM3 appears in the I/O space at 3E8h-3EFh and can be jumper selected to use IRQ5, IRQ6, or IRQ7.

By changing an internal configuration register in the Elan520, the serial clock to the COM ports can be switched to a 10 times rate (18.432 MHz). This feature allows baud rates higher than 115 Kbaud (such as 230K baud or 576K baud), as well as non-standard lower baud rates (such as 24 Kbaud). See Appendix G for further information.

The COM1 and COM2 ports may also be configured to use a DMA channel, which may be useful when very high baud rates are being used.

See the AMD Elan520 User's Manual for further details.

Serial Port Configuration Registers

Because both serial ports are 100% PC compatible, software written for the PC that accesses serial ports directly or through standard BIOS calls will work without modification on the TS-5400. The details of the COM port internal registers are available in most PC documentation books or the data sheet for the National Semiconductor NS16C550 may be consulted.

Serial Port Hardware

Figure 1 - COM2 Serial Port Header and DB9 Pin-out [signal direction is in brackets]

5V Power	10	5	GND
NC	9	4	DTR (RTS) [out]
[in] CTS	8	3	TX data [out]
[out] RTS	7	2	RX data [in]
NC	6	1	NC

Note:

The serial port headers use a non-standard numbering scheme. This was done so the header pins would have the same numbering as the corresponding DB-9 pin; i.e. pin 8 (CTS) on the header connects to pin 8 on the DB-9

Figure 2 - COM2 9-pin Sub D Pin-out [signal direction is in brackets]

		5	GND
Rx-	9	4	Rx+
[in] CTS	8	3	TX data [out]
[out] RTS	7	2	RX data [in]
Tx-	6	1	Tx+

Note:

COM1 has connections for the RS-232 port and the RS-485 port on the same 9 pin connector, only one of the two functions will be used at a time.

Each RS-232 serial port has 4 lines buffered: the Rx and Tx data lines and the CTS / RTS handshake pair. This is quite sufficient to interface with the vast majority of serial devices. If additional handshake lines are required, it will be necessary to add a TS-SER daughter board. The TS-5400 serial signals are routed to 10-pin header labeled COM2 and a standard 9-pin Sub-D male labeled COM2. A serial adapter cable can be plugged into the COM2 header to convert this into a standard DB9 male connector. The pin-outs for the 10-pin header and DB9 male connector are listed above. The RTS signal also drives the DTR pin on COM2, DTR is always the same state as RTS.

RS-485 Quick start procedure

1. The RS-485 option must be installed
2. Install FD jumper for full-duplex or HD for half-duplex RS-485 operation
3. Attach the RS-485 cable to the 9-pin Sub-D connector.
4. Set the COM1 UART serial parameters (baud rate, data, parity, and stop bits, interrupts, etc).
5. Run Auto485.exe utility (configures bits 6 and 7 at I/O 75h) (and initializes Timer2)
6. For Half-Duplex RTS mode: To transmit data, assert RTS and write the data to the UART. To receive data, deassert RTS and read the data from the UART
7. For Half-Duplex Automatic mode: just read or write data to the UART

An option is available to add support to COM1 for half duplex or full duplex RS-485. RS-485 drivers allow communications between multiple nodes up to 4000 feet (1200 meters) via twisted pair cable. Half-duplex RS-485 requires one twisted pair plus a Ground connection, while full duplex requires two twisted pair plus a Ground.

For half-duplex operation, a single twisted pair is used for transmitting and receiving. Bit 6 at I/O location 75h must be set to enable RTS mode or bit 7 can be set to enable Automatic mode. In RTS mode, the serial port RTS signal controls the RS-485 transmitter/receiver (See Automatic mode below). When RTS is asserted true, the RS-485 transmitter is enabled and the receiver disabled. When RTS is de-asserted the transmitter is tri-stated (disabled) and the receiver is enabled. Since the transmitter and receiver are never both enabled, the serial port UART does not receive the data transmitted.

For full-duplex operation, two twisted pairs are used and the transmitter can typically be left on all the time. Simply use RTS mode, and set RTS true.

See Figure 2 above for connector pin-outs.

Note:

The correct jumper (FD or HD) must be installed. See the Table 2 for details.

Fail-safe bias resistors are used to bias the TX+, TX- and RX+, RX- lines to the correct state when these lines are not being actively driven. This is an important consideration, since in a typical RS-485 installation, the drivers are frequently tri-stated. If fail-safe bias resistors are not present, the 485 bus may be floating and very small amounts of noise can cause spurious characters at the receivers. 4.7KW resistors are used to pull the TX+ and RX+ signals to 5V and also to bias the TX- and RX signals to ground. Termination resistors may be required for reliable operation when running long distances at high baud rates. Termination resistors should only be installed at each end of an RS-485 transmission line. In a multi-drop application where there are several drivers and/or receivers attached, only the devices at each end of the transmission line pair should have termination resistors.

A read at I/O location 75h bit 1 will return a "1" when the RS-485 option is installed.

Table 1 - COM1 Receiver Source

Jumper	Receiver Source
FD	Full-Duplex RS-485
HD	Half-Duplex RS-485
232	RS-232

Automatic RS-485 TX Enable

TS-5400 boards support fully automatic TX enable control. This simplifies the design of half-duplex systems since turning off the transmitter via the RTS signal is typically difficult to implement. The COM1 UART transmit holding register and the transmit shift register both must be polled until empty before deasserting RTS when using the RTS mode. The design gets more difficult when using the TX FIFO or when using a multi-tasking OS such as Linux.

In Automatic mode, Timer2 and a Xilinx PLD keep track of the bits shifting out the COM1 UART. This circuit automatically turns on/off the RS-485 transceiver at the correct times. This only requires the TIMER2 to be initialized once based on baud rate and data format, and bit 7 at I/O location 75 must be set. A utility called AUTO485.exe is included in the AUTOEXEC.bat that simplifies this task.

Configuring COM3

COM3 has a header labeled HD3 with 6 jumper positions. Three of these jumpers select which interrupt COM3 uses (IRQ5, IRQ6 or IRQ7). Only one of the interrupt jumpers should be installed. . Note: IRQ7 is used by many PCMCIA cards. The other three jumper positions select RS-232, RS-485 (Half- Duplex), or RS-422 (Full-Duplex) operation. Only one of these jumpers should be installed.

Linux strongly prefers the use of interrupts on all COM ports. If COM3 does not have a jumper installed for interrupt selection, extremely slow throughput is a common symptom under Linux. IRQ5 is the most commonly used IRQ for COM3. Regardless of IRQ selected, run the setserial command with the following parameters to register the interrupt with the kernel:

setserial -v /dev/ttyS2 auto_irq autoconfig

Adding Serial Ports

If your project requires more than three serial ports, additional ports may be added via the PC/104 expansion bus. Technologic Systems offers three different daughter boards (TS-SER1, TS-SER2, and TS-SER4) that add 1,2,or 4 extra COM ports respectively. Typically these would be configured as COM4 or be assigned other higher COM I/O locations. Because DOS only directly supports four serial ports, any additional ports beyond four will require software drivers if using DOS.

The TS-5500 PC/104 bus has IRQ 5, 6, 7, 12 or 15 available for additional serial ports.

Note:

IRQ7 is used by many PCMCIA cards and COM3 will typically use IRQ5 or IRQ6.

Typically each serial port has a dedicated interrupt, but the TS-SER4 allows all four extra serial ports to share a single interrupt. This is very helpful in systems with a large number of serial ports since there are a limited number of IRQ lines available.

Digital I/O

There are 38 Digital Input/Output (DIO) lines available on the TS-5500. These are available on 3 headers labeled DIO1, DIO2, and LCD. In addition to the DIO signals, each header also has 5 Volt power and Ground available, while the DIO2 header has an external reset available on pin 12.. The header labeled LCD can be used as 11 DIO lines or as an alphanumeric LCD interface (See Section 7).

24 of the DIO lines are arranged as three byte-wide ports that can be programmed as either inputs or outputs in groups of 4-bits. 8 more of the DIO lines can also be programmed as either inputs or outputs (in groups of 4-bits also). The remaining 6 lines have a fixed configuration of 5 inputs and 1 output. Two of the DIO lines can be programmed to cause interrupts.

DIO1 Header

Figure 2 - DIO1 Header Pinout

5V	16	15	DIO1_7
DIO1_13	14	13	DIO1_6
DIO1_12	12	11	DIO1_5
DIO1_11	10	9	DIO1_4
DIO1_10	8	7	DIO1_3
DIO1_9	6	5	DIO1_2
DIO1_8	4	3	DIO1_1
GND	2	1	DIO1_0

The DIO1 port provides +5V, GND, and 14 digital I/O lines that may be used to interface the TS-5500 with a wide range of external devices. DIO lines DIO1_0 thru DIO1_7 are a byte-wide port accessed at I/O location Hex 7B, while the 6 other DIO lines DIO1_8 thru DIO1_13 are accessed in the lower 6 bits of I/O location Hex 7C. I/O location Hex 7A is a control port for DIO1. The direction of DIO lines DIO1_0 thru DIO1_3 is controlled by bit 0 of I/O location Hex 7A, and the direction of DIO1_4 thru DIO1_7 is controlled by bit 1 of I/O location Hex 7A. The direction of DIO1_8 thru DIO1_11 is controlled by bit 5 of I/O location Hex 7A, while DIO1_12 and DIO1_13 are always inputs. In all cases, when a control bit is a �1�, it is setting the corresponding DIO lines to be Outputs, while a �0� sets them to be Inputs. All control bits at I/O location Hex 7A are initialized at reset to be �0�.

When bit 7 of I/O location Hex 7A is a �1�, DIO1_13 is connected to IRQ7 allowing this port to trigger an interrupt.

All digital outputs on this port can source 4 mA or sink 8 mA and have logic swings between 3.3V and ground. The digital inputs have standard TTL level thresholds and must not be driven below 0 Volts or above 5.0 Volts. DIO lines DIO1_0 thru DIO1_7 have 4.7KW pull-up resistors to 5V biasing these signals to a logic�1�.

DIO2 Header

Figure 4 - DIO2 Header Pinout

5V	16	15	DIO2_7
DIO2_13	14	13	DIO2_6
Reset#	12	11	DIO2_5
DIO2_11	10	9	DIO2_4
DIO2_10	8	7	DIO2_3
DIO2_9	6	5	DIO2_2
DIO2_8	4	3	DIO2_1
GND	2	1	DIO2_0

The DIO2 port provides +5V, GND, 13 digital I/O lines, and an external reset. DIO lines DIO2_0 thru DIO2_7 are a byte-wide port accessed at I/O location Hex 7E, while the 5 other DIO lines DIO2_8 thru DIO2_11 and DIO2_13 are accessed in bits 0-4 and bit6 respectively at I/O location Hex 7F. I/O location Hex 7D is a control port for DIO2. The direction of DIO lines DIO2_0 thru DIO2_3 is controlled by bit 0 of I/O location Hex 7D, and the direction of DIO2_4 thru DIO2_7 is controlled by bit 1 of I/O location Hex 7D. The direction of DIO2_8 thru DIO2_11 is controlled by bit 5 of I/O location Hex 7D, while DIO2_13 is always an input. In all cases, when a control bit is a �1�, it is setting the corresponding DIO lines to be Outputs, while a �0� sets them to be Inputs. All control bits at I/O location Hex 7D are initialized at reset to be �0�.

When bit 7 of I/O location Hex 7D is a �1�, DIO2_13 is connected to IRQ6 allowing this port to trigger an interrupt.

All digital outputs on this port can source 4 mA or sink 8 mA and have logic swings between 3.3V and ground. The digital inputs have standard TTL level thresholds and must not be driven below 0 Volts or above 5.0 Volts. DIO lines DIO1_0 thru DIO1_7 have 4.7KW pull-up resistors to 5V biasing these signals to a logic�1�.

Using LCD Port as Digital I/O

Figure 5 - Pinout for LCD header when used as DIO

LCD_6	14	13	LCD_7
LCD_4	12	11	LCD_5
LCD_2	10	9	LCD_3
LCD_0	8	7	LCD_1
LCD_WR	6	5	LCD_EN
Bias	4	3	LCD_RS
GND	2	1	5V

The LCD Port can be used as 11 additional digital I/O lines or it can be used to interface to a standard alphanumeric LCD display. At system reset, the port defaults to DIO mode. If using an LCD display this port can be switched to LCD mode by writing a �1� into bit 4 at I/O location Hex 7D, or the BIOS call to enable the LCD also sets bit 4 at I/O location Hex 7D (See Section 7 for LCD mode).

When the LCD port is in DIO mode, pins LCD_RS and LCD_WR are digital inputs, LCD_EN is a digital output, and LCD_0 thru LCD_7 are programmable as either inputs or outputs.

LCD_RS and LCD_WR can be read at I/O location 73h bits 7 and 6, respectively. The state of LCD_EN is controlled by writing to I/O location 73h bit 0.

LCD_0 thru LCD_7 can be read or written at I/O location 72h. The direction of this byte-wide port (pins 7 � 14) is determined by bits 2 and 3 at I/O location 7Dh. If bit 2 is a zero, then the lower 4 bits (pins 7 � 10) are inputs. If bit 2 is logic 1, then pins 7 � 10 are outputs. Bit 3 at location 7Dh controls the upper 4 bits, pins 11 � 14 in a like manner.

When bit 6 of I/O location Hex 7D is a �1�, LCD_RS is connected to IRQ1 allowing this port to trigger an interrupt.

All digital outputs on this port can source 4 mA or sink 8 mA and have logic swings between 3.3V and ground. The digital inputs have standard TTL level thresholds and must not be driven below 0 Volts or above 5.0 Volts. DIO lines DIO1_0 thru DIO1_7 have 4.7KW pull-up resistors to 5V biasing these signals to a logic�1�.

A/D Converter

The TS-5500 supports an optional eight-channel, 12-bit A/D converter (ADC) capable of 60,000 samples per second. Each channel is independently software programmable for a variety of analog input ranges: -10V to +10V, -5V to +5V, 0V to +10V, or 0V to +5V. This allows an effective dynamic range of 14 bits. Each channel is overvoltage tolerant from -16V to + 16V, and a fault condition on any channel will not affect the conversion result of the selected channel. This is all accomplished with a 5V only power supply; no negative supply voltage is required. The Maxim MAX197 chip can be replaced with a MAX199 chip if a lower range of analog input levels is required (-4V to +4V, -2V to +2V, 0V to 4V,and 0V to 2V).

Single Sample Acquisition Prcedure

An acquisition is initiated by writing to I/O location 196h. The value written to I/O location 196h determines the channel to convert (bits 0-2) and selects one of four input ranges (bits 3,4). Bits 5-7 should be set to zero. After the write cycle to I/O location 196h, the MAX197 completes the A/D conversion in 11 mS. Bit 0 at I/O location 195h may be polled to determine when the conversion is complete (zero = complete). The conversion result is now available at locations 196h (LSB) and 197h (MSB). A single word read at I/O 196h can also be used. When using unipolar modes, the result is in binary format with the upper 4 bits of the MSB equal to zero. When a bipolar mode is used, the result is in twos-complement binary with the upper 4 bits (Bits 12-15) equal to bit 11 (sign extended).

If more details on the A/D converter specifications are required, the Maxim web site is listed in Appendix G .

A/D Converter BIOS Call

An A/D acquisition can also be obtained through BIOS call int 15h, function B050h. By using a BIOS call, your code will operate safely even when running on a development machine without the ADC, because the function call will not "hang" if there is a hardware fault (MAX197 not populated). If the ADC completion bit is not true after 50 mS, the routine exits with an error condition.

Int 15h / Function B050h � ENTRY: AX = B050h BL = Value to write into A/D Control register (See Table 6) EXIT: CY = 0 (no error) AH = 0 � No Error 1 � bad subfunction 2 � bad input registers (i.e. if BL bit 5 set) 3 � ADC option not present (I/O 7Dh bit 0 = 0) 4 � Hardware error (A/D timeout) BX = A/D Conversion value

For Linux A/D driver information refer to the �Linux Developers Manual� on the Technologic Systems website: www.embeddedx86.com