TS-5600

TS-5600

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Introduction

The model TS-5600 is a compact, full-featured PC compatible Single Board Computer based on the AMD Elan520 processor. At 133 MHz, it is approximately 10 times faster than our other 386EX based products for only a small additional cost. PC compatibility allows for rapid development since you can use standard PC development tools such as Turbo C or Power Basic or Linux based tools as well. If you have done work in the PC world in the past, you will find you can now build applications for a very small target that does not require a keyboard, video, floppy disks, or hard drives.

By adding the optional TS-9500 daughter board, you can compile and debug directly on the TS-5600 with standard VGA video and keyboard interfaces. Alternatively, you can typically write and debug code on a host PC using standard development tools for the PC platform, then simply copy it to and run it on the TS-5600 without modification. If additional peripherals are required, the PC/104 expansion bus allows for many standard functions available off-the-shelf. It is also very simple to create a custom PC/104 daughter board for those special features that differentiate your product. Technologic Systems can provide technical support as well as a free quotation for any custom hardware, software, or BIOS modifications you may require.

This manual is fairly short. This is because for the most part, the TS-5600 is a standard x86-based PC compatible computer, and there are hundreds of books about writing software for the PC platform. The primary purpose of this manual is documenting where the TS-5600 differs from a standard PC.

PC Compatibility

PC compatibility requires much more than just an x86 processor. It requires PC compatible memory and I/O maps as well as a PC compatible BIOS. The General Software EMBEDDED BIOS offers a high degree of compatibility with past and present BIOS standards allowing it to run off-the shelf operating systems and application software.

The EMBEDDED BIOS has been tested with all major versions of DOS, including MS-DOS, DR-DOS, and Embedded DOS 6-XL; all major versions of OS/2, including MS-OS/2 and IBM OS/2; MS-Windows 3.1, Windows-95, Windows NT, and NetWare 386.

Operating Systems

Technologic Systems Embedded PCs are compatible with a wide variety of x86-based operating systems. A partial list OSes currently used with our boards by customers includes:

• TNT Embedded Toolsuite, Phar Lap Software
• UCos II
• RTKernel, On Time Software
• RTEMS, On-Line Applications Research Corporation
• DOS with WATTCP, public domain TCP/IP source code for DOS
• Linux

The TS-5600 is shipped, free of charge, with Embedded DOS ROM by General Software.

The TS-5600 can be shipped upon request with Linux pre-installed for a nominal fee. The Linux file system and kernel is also freely available on the web should you wish to install it yourself. Typically, the Linux OS requires a 32MB or larger Compact Flash or an M-System's DiskOnChip.

Power

The TS-5600 requires regulated 5VDC at 800 mA (typical maximum). When running the Linux OS, it will drop to about 300 mA during low usage. A quick release screw-down terminal block for the 5V power and power GND connections is provided for easy connection to an external power supply. When power is first supplied to the TS-5600, the board mounted LED is immediately turned on under hardware control. Once the processor begins execution, the LED is turned off. The LED then turns on then off to provide a characteristic blink during execution of POST. If the LED does not turn on at all, the most likely problem is the power supply. Check that the +5V and GND connections are not reversed. A diode protects the board against damage in such a situation, but it will not run. Please note that supply voltages over 6 VDC may damage the TS-5600. Be sure to use a regulated 5 VDC power supply, preferably with current limiting to 3 to 5 Amps. If using a PC power supply that may be capable of supplying 20 Amps or more, it is possible to do irreversible damage if the polarity on the power leads is reversed.

Memory

SDRAM

The TS-5600 has a total of 32 Megabytes (MB) of high-speed SDRAM providing 640 Kilobytes (KB) of base memory, 31 MB of extended memory, and 128 KB of shadow RAM for the BIOS. This is identical to a standard PC memory map. The TS-5600 can be ordered with 64MB of SDRAM, but it is not field upgradeable. The TS-5600 SDRAM chips are soldered directly to the board. By not using a SIMM socket, the TS- 5600 is much more reliable in high-vibration environments.

Flash

There is a total of 2 MB of Flash memory on the TS-5600 with 128 KB reserved for the BIOS. During POST, this 128 KB area is copied from Flash into SDRAM at addresses E0000h through FFFFFh for improved performance (a standard technique known as BIOS Shadowing). The remainder of the Flash memory (1920 KB) is configured as a solid-state disk (SSD) drive appearing as drive A. Drive A is fully supported by the BIOS as an INT 13h drive. The physical Flash memory is accessed by the BIOS in protected mode at memory address 148M. The Flash memory is guaranteed capable of a minimum of 100,000 write/erase cycles. This means that if you completely erase and rewrite the SSD drive 10 times a day you have over 27 years before any problems would occur. Reading the SSD produces no wear at all. Power failure during flash writes can cause corruption of flash drive FAT tables (A: or B:). Therefore applications writing frequently should use a Compact Flash card drive which is much more tolerant of power failures during write cycles. Flash drive A is read-only when JP3 is not installed. Removing JP3 also makes the 128 kbyte BIOS area of the Flash write protected as well. Write protecting the A: drive can be useful if there are critical files in the final product that must be very secure.

Compact Flash cards

If 2MB of Flash is insufficient for your application, additional non-volatile storage can be added with a Compact Flash (CF) card. CF cards can supply additional storage that will behave much as a hard drive does in a typical PC with sizes ranging from 8MB to 512MB. These products are inherently more rugged than a hard drive since they are completely solid-state with no moving parts.

The Compact Flash card has the added advantage of being removable media. A SanDisk USB Compact Flash reader/writer (which is included in the TS-5600 Developer's Kit) is recommended for the host PC for file transfers. This results in the ability to quickly move files from a host PC to the TS-5600 using a Compact Flash card as the removable media. Since the Compact Flash card appears as a standard IDE drive on the TS-5600, it uses no additional RAM for drivers. While a USB Compact Flash reader allows for hot swapping of the Compact Flash card on the host PC, the Compact Flash interface on the TS-5600 is not hot swappable, the TS-5600 must be rebooted after removing or installing a Compact Flash card.

Using the SanDisk USB Compact Flash Card Reader

This device allows for a very fast and reliable method of moving files between the host PC and target SBC (TS-5600). The Compact Flash (CF) card can then be hot swapped (inserted or removed without rebooting the host PC). Sometimes it is necessary to unplug the USB cable and reinstall it after swapping CF cards (at least Windows ME seems to prefer this).

Note:

The TS-5600 always needs to be powered off before swapping CF cards.

Non-Volatile SRAM

An optional 32 KB of non-volatile SRAM memory can be installed into the TS-5600. This behaves exactly like battery-backed SRAM. Non-volatile SRAM provides non-volatile memory with unlimited write cycles and no write time degradation, unlike Flash memory. The SRAM uses an additional 32 KB memory range of D0000h through D7FFFh. If the SRAM is installed, PC/104 daughter card that uses memory mapped I/O must not conflict with this address range.

Serial Ports

The two PC compatible asynchronous serial ports (COM1 and COM2) provide a means to communicate with external serial devices such as printers, modems, etc. Each is independently configured as a standard PC COM port that is compatible with the National Semiconductor NS16C450. Alternatively, these ports can be changed to the 16C550 mode with 16 byte FIFOs in both the receive and transmit UART channels. COM1 appears in the I/O space at 3F8h - 3FFh and uses IRQ4. COM2 is located at 2F8h - 2FFh and uses IRQ3.

By changing an internal configuration register in the Elan520, the serial clock to the COM ports can be switched to a 10 times rate (18.432 MHz). This feature allows baud rates higher than 115 Kbaud (such as 230K baud or 576K baud), as well as non-standard lower baud rates (such as 24 Kbaud). See Appendix G for further information.

The COM1 and COM2 ports may also be configured to use a DMA channel, which may be useful when very high baud rates are being used.

See the AMD Elan520 User's Manual for further details.

Serial Port Configuration Registers

Because both serial ports are 100% PC compatible, software written for the PC that accesses serial ports directly or through standard BIOS calls will work without modification on the TS-5600. The details of the COM port internal registers are available in most PC documentation books or the data sheet for the National Semiconductor NS16C550 may be consulted. See the AMD Elan520 User's Manual for further details.

Serial Port Hardware

The COM2 RS-232 port has 7 signals supported: RXD, TXD, RTS, CTS, DTR, DSR, and DCD. This port can interface to almost any RS-232 device. The COM1 RS-232 serial port has 4 signals supported: RXD, TXD, RTS and CTS. This is quite sufficient to interface with the vast majority of serial devices. The TS-5600 COM ports are accessable on two 10-pin Headers labeled COM1 and COM2. Adaptor cables are available to convert these into standard 9-pin Sub-D male connectors.

Figure 1 - COM2 Serial Port Header Pin-out

5V Power	10	5	GND
NC	9	4	DTR [out]
[in] CTS	8	3	TXD [out]
[out] RTS	7	2	RXD [in]
[in] DSR	6	1	DCD [in]

Note:

The serial port headers use a non-standard numbering scheme. This was done so the header pins would have the same numbering as the corresponding DB-9 pin; i.e. pin 8 (CTS) on the header connects to pin 8 on the DB-9

Figure 2 - COM1 Serial Port Header Pin-Out

5V Power		5	GND
Rx-	9	4	Rx+
[in] CTS	8	3	TX data [out]
[out] RTS	7	2	RX data [in]
Tx-	6	1	Tx+

Note:

COM1 has connections for the RS-232 port and the RS-485 port on the same 9 pin connector, only one of the two functions will be used at a time.

The pin-outs for the COM1 and COM2 10-pin headers are listed above. When using COM1 in the RS-232 mode, be sure that the jumper labeled "232" is installed.

RS-485 Quick start procedure

1. The RS-485 option must be installed
2. Install FD jumper for full-duplex or HD for half-duplex RS-485 operation
3. Attach the RS-485 cable to the 10-pin Header - Adaptor cables to Sub-DB9 connector are available from Technologic Systems
4. Set the COM1 UART serial parameters (baud rate, data, parity, and stop bits, interrupts, etc).
5. Run Auto485.exe utility (configures bits 6 and 7 at I/O 75h) (and initializes Timer2)
6. For Half-Duplex RTS mode: To transmit data, assert RTS and write the data to the UART. To receive data, deassert RTS and read the data from the UART
7. For Half-Duplex Automatic mode: just read or write data to the UART

An option is available to add support to COM1 for half duplex or full duplex RS-485. RS-485 drivers allow communications between multiple nodes up to 4000 feet (1200 meters) via twisted pair cable. Half-duplex RS-485 requires one twisted pair plus a Ground connection, while full duplex requires two twisted pair plus a Ground. For half-duplex operation, a single twisted pair is used for transmitting and receiving. Bit 6 at I/O location 75h must be set to enable RTS mode or bit 7 can be set to enable Automatic mode. In RTS mode, the serial port RTS signal controls the RS-485 transmitter/receiver (See Automatic mode below). When RTS is asserted true, the RS-485 transmitter is enabled and the receiver disabled. When RTS is de-asserted the transmitter is tri-stated (disabled) and the receiver is enabled. Since the transmitter and receiver are never both enabled, the serial port UART does not receive the data transmitted. For full-duplex operation, two twisted pairs are used and the transmitter can typically be left on all the time. Simply use RTS mode, and set RTS true. See Figure 2 above for connector pin-outs.

Note:

The correct jumper (FD or HD) must be installed.

See the Table 2 for details. Fail-safe bias resistors are used to bias the TX+, TX- and RX+, RX- lines to the correct state when these lines are not being actively driven. This is an important consideration, since in a typical RS-485 installation, the drivers are frequently tri-stated. If fail-safe bias resistors are not present, the 485 bus may be floating and very small amounts of noise can cause spurious characters at the receivers. 4.7KW resistors are used to pull the TX+ and RX+ signals to 5V and also to bias the TX- and RX- signals to ground. Termination resistors may be required for reliable operation when running long distances at high baud rates. Termination resistors should only be installed at each end of an RS-485 transmission line. In a multi-drop application where there are several drivers and/or receivers attached, only the devices at each end of the transmission line pair should have termination resistors. A read at I/O location 75h bit 1 will return a "1" when the RS-485 option is installed.

Table 1 - COM1 Receiver Source

Jumper	Receiver Source
FD	Full-Duplex RS-485
HD	Half-Duplex RS-485
232	RS-232

Automatic RS-485 TX Enable

TS-5600 boards support fully automatic TX enable control. This simplifies the design of half-duplex systems since turning off the transmitter via the RTS signal is typically difficult to implement. The COM1 UART transmit holding register and the transmit shift register both must be polled until empty before deasserting RTS when using the RTS mode. The design gets more difficult when using the TX FIFO or when using a multi-tasking OS such as Linux. In Automatic mode, Timer2 and a Xilinx PLD keep track of the bits shifting out the COM1 UART. This circuit automatically turns on/off the RS-485 transceiver at the correct times. This only requires the TIMER2 to be initialized once based on baud rate and data format, and bit 7 at I/O location 75 must be set. A utility called AUTO485.exe is included in the AUTOEXEC.bat that simplifies this task.

Adding Serial Ports

If your project requires more than two serial ports, additional ports may be added via the PC/104 expansion bus. Technologic Systems offers three different daughter boards (TS-SER1, TS-SER2, and TS-SER4) that add 1,2,or 4 extra COM ports respectively. Typically these would be configured as COM3 or be assigned other higher COM I/O locations. Because DOS only directly supports four serial ports, any additional ports beyond four will require software drivers if using DOS. The TS-5600 PC/104 bus has IRQ 5, 6, 7, 9, 12 or 15 available for additional serial ports.

Note:

IRQ7 is used by many PCMCIA cards.

Typically each serial port has a dedicated interrupt, but the TS-SER4 allows all four extra serial ports to share a single interrupt. This is very helpful in systems with a large number of serial ports since there are a limited number of IRQ lines available.

Digital I/O

There are 23 Digital Input/Output (DIO) lines available on the TS-5600. These are available on two headers labeled DIO and LCD. In addition to the DIO signals, each header also has 5 Volt power and Ground available, while the DIO header has an external reset available on pin 12 and IRQ6 in available on pin 13. The header labeled LCD can be used as 11 DIO lines or as an alphanumeric LCD interface (See Section 7). Most of the DIO lines are arranged as byte-wide ports that can be programmed as either inputs or outputs in groups of 4-bits.

Four of the DIO lines are dedicated 0-5V swing outputs with high current drive capability. Two of these outputs can sink or source 25 mA, while the other two can sink or source 100 mA. The 5V power output pins on these headers have a 750 mA Poly-Fuse to prevent excessive current.

DIO Header

Figure 2 - DIO Header Pinout

5V	16	15	DIO_7
IRQ6	14	13	DIO_6
Reset#	12	11	DIO_5
DIO_11	10	9	DIO_4
DIO_10	8	7	DIO_3
DIO_9	6	5	DIO_2
DIO_8	4	3	DIO_1
GND	2	1	DIO_0

The DIO port provides +5V, GND, and 12 digital I/O lines that may be used to interface the TS-5600 with a wide range of external devices. DIO lines DIO_0 thru DIO_7 are a byte-wide port accessed at I/O location Hex 7E, while the 4 other DIO lines DIO_8 thru DIO_11 are accessed in the lower 4 bits of I/O location Hex 7F. I/O location Hex 7D is a control port for DIO. The direction of DIO lines DIO_0 thru DIO_3 is controlled by bit 0 of I/O location Hex 7D, and the direction of DIO_4 thru DIO_7 is controlled by bit 1 of I/O location Hex 7D. The DIO_8 thru DIO_11 lines are always outputs. In all cases, when a control bit is a "1", it is setting the corresponding DIO lines to be Outputs, while a "0" sets them to be Inputs. All control bits at I/O location Hex 7D are initialized at reset to be "0".

The DIO_0 thru DIO_7 digital outputs on this port can source 4 mA or sink 8 mA and have logic swings between 3.3V and ground. The digital inputs have standard TTL level thresholds and must not be driven below 0 Volts or above 5.0 Volts. DIO lines DIO_0 thru DIO_5 have 4.7KW pull-up resistors to 5V biasing these signals to a logic"1". DIO_6 and DIO_7 are not biased and may float to either state when configured as Inputs, if not being actively driven.

DIO_10 and DIO_11 outputs have very high current drivers and can source or sink 100 mA each.

DIO_8 and DIO_9 outputs can source or sink 25 mA. DIO_8 thru DIO_11 all swing between 0 and 5V. Pin 14 on the DIO header is connected directly to IRQ6 (also available on the PC/104 bus). Pin 12 is an active low reset signal. It has a 4.7K pull-up resistor to 5V. A logic low on this signal will cause a hard reset to the TS-5600 (same as a power cycle). It is possible change the DIO_11 output so that it is driven by the Timer2 signal. The Timer2 signal has historically been used to drive the speaker in a PC. The DIO_11 output has 100 mA source and sink drive capability, so it could be used to directly drive a small 8 ohm speaker if a series capacitor is used to block the DC component and a series resistor is added to reduce the power out. A 47 uF capacitor and a 27 ohm resistor is a good starting point (adjust the resistor for volume). If bit 2 at I/O location Hex 79 is set, Timer2 will drive the DIO_11 output (instead of bit 3 at I/O location Hex 7F).

Using LCD Port as Digital I/O

The LCD Port can be used as 11 additional digital I/O lines or it can be used to interface to a standard alphanumeric LCD display. At system reset, the port defaults to DIO mode. If using an LCD display this port can be switched to LCD mode by writing a "1" into bit 4 at I/O location Hex 7D, or the BIOS call to enable the LCD also sets bit 4 at I/O location Hex 7D (See Section 8 for LCD mode).

Figure 5 - Pinout for LCD header when used as DIO

LCD_6	14	13	LCD_7
LCD_4	12	11	LCD_5
LCD_2	10	9	LCD_3
LCD_0	8	7	LCD_1
LCD_WR	6	5	LCD_EN
Bias	4	3	LCD_RS
GND	2	1	5V

When the LCD port is in DIO mode, pins LCD_RS and LCD_WR are digital inputs, LCD_EN is a digital output, and LCD_0 thru LCD_7 are programmable as either inputs or outputs. LCD_RS and LCD_WR can be read at I/O location 73h bits 7 and 6, respectively. The state of LCD_EN is controlled by writing to I/O location 73h bit 0. LCD_0 thru LCD_7 can be read or written at I/O location 72h. The direction of this byte-wide port (pins 7 - 14) is determined by bits 2 and 3 at I/O location 7Dh. If bit 2 is a zero, then the lower 4 bits (pins 7 - 10) are inputs. If bit 2 is logic 1, then pins 7 - 10 are outputs. Bit 3 at location 7Dh controls the upper 4 bits, pins 11 - 14 in a like manner. All digital outputs on this port can source 4 mA or sink 8 mA and have logic swings between 3.3V and ground. The digital inputs have standard TTL level thresholds and must not be driven below 0 Volts or above 5.0 Volts. The 5V power has a 750 mA Poly-Fuse to limit the current.

Analog Inputs and Outputs

The TS-5600 supports an optional 8-channel, 12-bit A/D converter (ADC) and an optional 2-channel 12-bit Digital-to-Analog converter (DAC).

The A/D converter has a conversion time of 8 microseconds. Six of these channels (1-6) are available on the Analog Header. Channel # 7 monitors the 5V power on the TS-5600 while channel # 8 is connected to ground. The ADC is based on an Analog Devices AD7888 chip and uses a Texas Instruments LT1009 for the precision 0.2% reference voltage. The AD7888 chip has eight analog inputs with a 0-2.5V range. Analog channels 4-6 on the TS-5600 have a 0-2.5V analog input range. Analog channels 1-3 use resistor dividers to obtain 0-10V analog input ranges. All of the analog channels have a 100 nF capacitor at each analog input of the AD7888 chip. This creates a low pass filter with a bandwidth of approximately 500 Hz.

Channel # 7 has 6.19K and 4.32K ohm resistors creating a voltage divider being driven by the on-board TS-5600 5V supply. This divider results in 41.1% of 5V supply voltage driving the AD7888 analog input. If the 5V supply were exactly 5.000 Volts, this would result in the ADC reporting 82.2% of a full-scale reading. Put another way, a full-scale reading on the ADC would indicate that the 5V supply is at 6.083 Volts.

SPI Interface

The SPI bus is a three-wire interface that allows high-speed serial communications using low-pin count peripherals. The A/D converter and the DAC chip are both accessed using the SPI bus. The SPI bus is a byte-oriented bus, so 16-bit transfers (required by the A/D and DAC chips) need to use two back-toback byte transfer cycles. The SPI bus details are presented in Section 12.

A/D Converter Interface

The AD7888 chip uses the SPI bus for all data transfers. Prior to accessing the AD7888, the SPI control register must be set to Hex 21. This sets the SPI bus for the following format:

• 2 MHz clock rate
• Clock idle state is high
• Non-inverted phase
• MSB shifted first

Then the Chip Select for the AD7888 chip must be asserted low. The Elan520 DIO pin PIO27 controls the chip select to the AD7888. PIO27 can be set to a low state by writing a Hex 0800 to memory location Hex DFC3A.

An acquisition is initiated by sending a 16-bit word to the AD7888. The exact format of this 16-bit word is described below. To start the acquisition, the 8-bits of the command byte must be loaded into the SPI TX register, then a Hex 03 written into the SPI Command register will cause the MS byte to be sent to the AD7888. The SPI Status register bit 1 must be polled until it is zero to indicate the MS byte transfer is complete (takes about 4 microseconds with the 2 MHZ clock). The RX data (MS byte) should be read at this time and stored, and then a zero should be written into the TX register, and again a Hex 03 is written into the SPI Command register. The SPI Status register bit 1 must be polled until it is zero to indicate the LS byte transfer is complete. Then the RX data register can be read to get the LS byte returned from the AD7888. When all A/D acquisitions are completed, the Chip Select for the AD7888 must be deasserted by setting PIO27 to a logic high.

The 16-bits of RX data received is the A/D conversion result. The four MS bits are always zero and the lower 12-bits represents the analog value of the sampled channel. The total time for a single acquisition is approximately 8 microseconds.

The command byte that is sent to the AD7888 chip determines how the next acquisition is taken. The command byte is the first 8-bit quantity sent to the AD7888. Bits 3-5 determine which of the 8-channels is sampled, and bit 2 determines whether the internal or external reference is used. Bit 2 should always be set to “1” to indicate an external reference is to be used.

Due to the design of the AD7888 chip, it is not possible to select the channel to convert and also convert the selected channel in a single 8 microsecond acquisition cycle. The AD7888 uses a pipelined architecture where the channel being converted is determined by the value of bits 3-5 for the previous cycle. This means that to sample a random analog channel, it will require two complete cycles, the first cycle to get the desired channel selected, and the second cycle to acquire the analog value. In most cases, this is not necessary, since you will always be sampling a known set of channels and can create an algorithm that pipelines the acquisitions.

A Linux driver has been written for the A/D converter, the Linux A/D driver with full “C” source code can be found on our website. Refer to the “Linux Developers Manual” on the Technologic Systems website: www.embeddedx86.com

DAC Converter Interface

The DAC uses a Texas Instruments TLV5618A chip with a 3 microsecond conversion time. It has two 12-bit DAC outputs that have an analog voltage range of 0-5V. The DAC also uses the same Texas Instruments LT1009 for the precision 0.2% reference voltage that is used for the A/D converter.

The TLV5618A chip uses the SPI bus for all data transfers. Prior to accessing the TLV5618A, the SPI control register must be set to Hex 03. This sets the SPI bus for the following format:

• 8 MHz clock rate
• Clock inverted (idle state = 0)
• Non-inverted phase (data latched on falling edges)
• MSB shifted first

Then the Chip Select for the TLV5618A chip must be asserted low. The Elan520 DIO pin PIO15 controls the chip select to the AD7888. PIO15 can be set to a low state by writing a Hex 8000 to memory location Hex C30.

Any write to the DAC register will initiate a DAC cycle with the lower 12-bits being the value written into one of the two DAC channels or into a buffer register. Bits 14,15 select the DAC channel (1-4) to be written into. Bit 13 allows the DAC value to be written into a Buffer register inside the TLV5617 chip. This buffer register acts as temporary holding register. This special cycle is implemented to allow for a simultaneous update of two DAC channels. For example, if the Bit 13 is set and Bit 15 is clear, then the DAC cycle will update the buffer in the TLV5617, but will not change any analog output. Then when a DAC cycle is run writing to Channel 2, Channel 1 will be updated with the holding register value. Both Channel 1 and Channel 2 analog outputs will change at exactly the same time. Channels 3 and 4 can also implement this simultaneous update in the same manner except Bit 15 must be set for the buffer write cycle. If simultaneous updates are not required, always leave bit 13 clear and simply select one of the four channels with bits 14 and 15.

Bit 12 set selects a fast settling time of about 3 microseconds, while Bit 12 clear will select a slower 10 microseconds. Consult the TLV5618 data sheet for details. When using the slow settling mode, the analog output has a slighter greater current sink and source capability. So this may be more desirable than the faster settling time.

A Linux driver has been written for the DAC, the Linux DAC driver with full “C” source code can be found on our website. Refer to the “Linux Developers Manual” on the Technologic Systems website: www.embeddedx86.com

LCD Interface

A 14-pin LCD connector is provided on the TS-5600 for interfacing with standard alphanumeric LCD displays. These displays use a common controller, the Hitachi HD44780 or equivalent. While software written for the HD44780 will work with all displays using the controller, the cable needed is dependent on the display used. For most displays, a straight-through type ribbon cable can be used. The connector on the LCD display is typically mounted on the backside of the display.

Warning – using an incorrect cable or mounting the LCD connector on the front-side can result in a reverse power polarity and can damage the LCD display. Please refer to your LCD data sheets for indepth information.

The TS-5600 BIOS incorporates a fairly complete set of INT10h video routines that work with the LCD. Once the LCD has been enabled (INT15h/Func B042h – see Appendix E below)

The LCD can be written to as the standard I/O device. This means that software can be developed and debugged using standard I/O calls, and the executable will work with LCD, VGA video, or redirected COM port. See the section 16 for more information.

I/O addresses 72h and 73h are used to access the LCD. Figure 6 shows the header pin-out, while Table 3 lists the LCD signals. The section below will briefly describe the LCD interface signals. The LCD can be controlled directly by software at these addresses.

The register select signal is simply the buffered A0 address line. Thus, reads and writes to 72h cause register select to be low, and those to 73h cause it to be high. Generally the LCD uses this line to separate data bytes from command bytes. See your LCD data sheet for details.

The LCD Write# signal is an active low write enable line.

LCD Enable is an active high signal, raised whenever the LCD addresses are being read or written.

D0 – D7 are bi-directional, buffered copies of the data bus and carry all data and commands to the LCD.

Table 3 is not the standard pin-outs given for LCD displays. But this pin-out allows a standard ribbon cable to be used when the ribbon cable is attached to the backside of the LCD.

Example LCD code is available at: ftp://ftp.embeddedarm.com/old/downloads/UTIL.ZIP

Matrix Keypad Support

The DIO2 port, signals DIO_0 through DIO_7, may be configured to support a 4 x 4 matrix keypad. When enabled, BIOS firmware performs all the work, making the matrix keypad appear as a simple 16- key keyboard to software. This allows the use of standard keyboard access routines. The default set of keys translated by the BIOS consists of 0 – 9, A – D, *, and #. The # key is returned as an ASCII Carriage Return character (Hex 0D). Because the user is writing the software, this set of keys is usually sufficient. However, a custom translation table can be loaded, allowing the use of function keys, arrow keys, or any other key on the keyboard.

Matrix keypad support is enabled or disabled using INT15h, Function B040h (see Appendix F). Once enabled, standard keyboard BIOS functions are enabled. Note that console redirection and the matrix keypad support are mutually exclusive – console redirection must be disabled to use the keypad.

A matrix keypad can be used with console redirection only if the keypad is not used as stdin, but read from as a hardware device. This is useful if one wishes to use console redirection or to use a keyboard as stdin. See section 16 for an explanation of console I/O and redirection. See the Technologic Systems download page for example code.

ftp://ftp.embeddedarm.com/old/downloads/KEYPAD.ZIP

When using a matrix keypad, the DIO signals DIO_0 through DIO_7 are not available as general I/O.

A Linux driver has been written for the Matrix Keypad, the Linux driver with full “C” source code can be found on our website. Refer to the “Linux Developers Manual” on the Technologic Systems website: www.embeddedx86.com

The 10/100 Base-T Ethernet Port

The TS-5600 has a full-function IEEE 802.3 (10/100 Mbit/sec) Ethernet port provided by Davicom DM9102A Ethernet controllers. The DM9102A is a single-chip, 32-bit PCI Ethernet controller that includes such features as full-duplex operation, power saving shutdown modes, LED indicators for link status/activity (Green) and auto-sense network speed detection (Amber). The physical interface is 10/100Base-T (RJ45 connector).

The TS-5600 has both a LINK/ACTIVITY LED and a 10/100 speed LED built into each RJ-45 connector that indicates the current Ethernet status. The LINK LED (left side of connector, green) is active when a valid Ethernet link is detected. This LED should be ON whenever the TS-5600 is powered on and properly connected to a 10/100BaseT Ethernet network. The LINK/ACTIVITY LED will blink to indicate network activity either inbound or outbound. The SPEED LED (right side of connector, amber) will be on when a 100 Mbit network is detected and off for a 10 Mbit network. Both of these LEDs are controlled by the DM9102A and do not require initialization by the processor.

LINUX TCP/IP configuration

When using the TS-5600 with TS-Linux, the DM9102A driver can be included in the kernel or loaded as a kernel module. If the Technologic Systems kernel is used, the DM9102A driver is built into the kernel. The settings stored in EEPROM on the TS-5600 are used to configure the DM9102A.

The TCP/IP settings for the TS-Linux are configured in the file ‘/etc/sysconfig/ifcfg-eth0’, here is a listing:

DEVICE=eth0 # Name of Ethernet interface
IPADDR=192.168.0.50 # IP address of this Ethernet interface.
NETMASK=255.255.255.0 # Used with NETWORK to determine local IP’s.
NETWORK=192.168.0.0 # Used with NETMASK to determine local IP’s.
BROADCAST=192.168.0.255 # Broadcast IP for system wide messages.
ENABLE=yes # Initialize on startup

The TCP/IP network settings are configured in the file ‘/etc/sysconfig/network_cfg’, here is a listing:

### Technologic Systems
### General Network Configuration File
###
NETWORKING=yes
GATEWAY=192.168.0.1 # Gateway for internet access
GW_DEV=eth0 # Gateway device to use
Hostname="miniepc.embeddedx86.com" # Host name for this computer
BOOTPROTO=no
DEFRAG_IPV4=no
FORWARD_IPV4=no

The TCP/IP name resolution server is configured in the file ‘/etc/resolv.conf’, here is a listing:

Nameserver 192.168.0.1 # Name server for domain name lookups.

To access the web server, open a web browser and enter “192.168.0.50” as the address. This should display the sample web page which demonstrates some of the functionality of Apache with PHP. Use the “ifconfig” command at the bash prompt to display the status of the Ethernet ports.

DOS TCP/IP configuration – Packet Driver and WATTCP

A standard packet driver for DOS is installed on the board as shipped, along with sample network applications written with the public domain Waterloo TCP/IP software (WATTCP). WATTCP is a freely available package (including source code) that provides TCP/IP connectivity for programs written for the DOS environment. See the Technologic Systems download page

ftp://ftp.embeddedarm.com/old/downloads/wat2001t.zip

In addition, we have written a simple DOS HTTP web server using WATTCP that is included on the TS- 5600 utility disk. The simple web server uses CGI calls to control a DIO pin from a web browser. Full source code is included, and you are free to modify and extend the code for your own use on Technologic Systems Single Board Computers.

The DOS packet driver (DM9PCIPD.COM) is loaded by AUTOEXEC.BAT once DOS starts. Hardware settings are read from the EEPROM chips and used by the packet driver to initialize each DM9102A. Below is an example of the DOS command line to load a packet driver for the Ethernet interface:

DM9PCIPD 0X60

The TCP/IP settings for the WATTCP code are stored in the WATTCP.CFG configuration file in the A:\ETHERNET directory, this file must be modified for the network environment where the TS-5600 will be installed.

WATTCP.CFG configuration file

my_ip=192.168.0.20 // IP address of this Ethernet interface.
hostname="epc.embeddedx86.com" // Host name of this computer.
netmask=255.255.255.0 // Used to determine which IP’s are local.
gateway=192.168.0.1 // Gateway for internet access.
nameserver=192.168.0.1 // Name server for domain name lookups.

With the WATTCP.CFG file properly setup and the 10/100 base-T cable connected, you should be able to ping other nodes on the network, i.e. ‘ping www.embeddedx86.com’

Other WATTCP examples include: serial to telnet redirector, http file download, telnet server, and finger, web server with I/O control . Many more can be downloaded from the internet as freeware.

DOS TCP/IP configuration – MS Client for DOS

The Davicom Ethernet adapter has the MS Client for DOS driver available. This has been tested and found to work on Windows workgroups as well as Samba workgroups. Check the Technologic Systems web page for driver downloads (www.embeddedx86.com).

Email support@embeddedx86.com with questions.

Product Notes

FCC Advisory

This equipment generates, uses, and can radiate radio frequency energy and if not installed and used properly (that is, in strict accordance with the manufacturer's instructions), may cause interference to radio and television reception. It has been type tested and found to comply with the limits for a Class A digital device in accordance with the specifications in Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference, in which case the owner will be required to correct the interference at his own expense.

If this equipment does cause interference, which can be determined by turning the unit on and off, the user is encouraged to try the following measures to correct the interference:

Reorient the receiving antenna. Relocate the unit with respect to the receiver. Plug the unit into a different outlet so that the unit and receiver are on different branch circuits. Ensure that mounting screws and connector attachment screws are tightly secured. Ensure that good quality, shielded, and grounded cables are used for all data communications. If necessary, the user should consult the dealer or an experienced radio/television technician for additional suggestions. The following booklets prepared by the Federal Communications Commission (FCC) may also prove helpful:

How to Identify and Resolve Radio-TV Interference Problems (Stock No. 004-000-000345-4) Interface Handbook (Stock No. 004-000-004505-7) These booklets may be purchased from the Superintendent of Documents, U.S. Government Printing Office, Washington, DC 20402.

Limited Warranty

See our Terms and Conditions for more details.