TS-7180 FPGA: Difference between revisions
From embeddedTS Manuals
(removed the 7 from bit 17 to make bit 1 on GPIO Output Data.) |
(Point to GPIO as the recommended way to access the FPGA's GPIO pins.) |
||
| Line 1: | Line 1: | ||
The TS-7180 | The recommended way to access the TS-7180's forty-four GPIO registers is with Linux's <code>gpioset</code> and <code>gpioget</code> commands (see: [[TS-7180 DIO|GPIO]]). | ||
The FPGA is available at I2C addresses 0x28-0x2f. First write the address which is | Internally, the TS-7180 accesses its FPGA registers over I2C. You should only need to do this in programming environments that lack access to proper GPIO interfaces like the one mentioned above. The supplied <code>tshwctl</code> utility may be used to access these registers; run <code>tshwctl -h</code> to see how to use it. | ||
The FPGA is available at I2C addresses 0x28-0x2f. First write the address (which is '''two''' bytes wide), followed by the data, which is one byte. | |||
The tables below list all the registers and their functions. | The tables below list all the registers and their functions. | ||
| Line 91: | Line 93: | ||
In the above table the GPIO uses are listed in the table below. | In the above table the GPIO uses are listed in the table below. | ||
== FPGA GPIOs == | |||
{| class="wikitable sortable" | {| class="wikitable sortable" | ||
Revision as of 17:15, 1 November 2021
The recommended way to access the TS-7180's forty-four GPIO registers is with Linux's gpioset and gpioget commands (see: GPIO).
Internally, the TS-7180 accesses its FPGA registers over I2C. You should only need to do this in programming environments that lack access to proper GPIO interfaces like the one mentioned above. The supplied tshwctl utility may be used to access these registers; run tshwctl -h to see how to use it.
The FPGA is available at I2C addresses 0x28-0x2f. First write the address (which is two bytes wide), followed by the data, which is one byte.
The tables below list all the registers and their functions.
| Address | Bits | Description | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0-43 | 7:3 | Reserved (Write 0) | |||||||||||||
| 2 | GPIOn Input Data | ||||||||||||||
| 1 | GPIOn Output Data | ||||||||||||||
| 0 | GPIOn Output Enable | ||||||||||||||
| 307 | 7:3 | Reserved (Write 0) | |||||||||||||
| 2:0 | Cell-modem uart selector
| ||||||||||||||
| 308 | 7:3 | Reserved (Write 0) | |||||||||||||
| 2:0 | HD1 uart selector
| ||||||||||||||
| 309 | 0 | PWM control[1] |
- ↑ Write 1 to this address to route the cpu PWM to DIO_1
In the above table the GPIO uses are listed in the table below.
FPGA GPIOs
| IO Number | Pad | Direction |
|---|---|---|
| 0 | WIFI_RESET# | OUT |
| 1 | EN_WIFI_PWR | OUT |
| 2 | EN_YEL_LED# | OUT |
| 3 | EN_GREEN_LED# | OUT |
| 4 | EN_RED_LED# | OUT |
| 5 | EN_BLUE_LED# | OUT |
| 6 | EN_CL_1 | OUT |
| 7 | EN_CL_2 | OUT |
| 8 | EN_CL_3 | OUT |
| 9 | EN_CL_4 | OUT |
| 10 | EN_ADC1_10V | OUT |
| 11 | EN_ADC2_10V | OUT |
| 12 | EN_ADC3_10V | OUT |
| 13 | EN_ADC4_10V | OUT |
| 14 | EN_SD_POWER | OUT |
| 15 | EN_USB_HOST_5V | OUT |
| 16 | EN_OFF_BD_5V | OUT |
| 17 | EN_CELL_MODEM_PWR | OUT |
| 18 | EN_NIMBEL_3.3V | OUT |
| 19 | EN_GPS_PWR# | OUT |
| 20 | EN_CAN_XVR# | OUT |
| 21 | EN_232_XVR | OUT |
| 22 | EN_LS_OUT_1 | OUT |
| 23 | EN_LS_OUT_2 | OUT |
| 24 | EN_LS_OUT_3 | OUT |
| 25 | EN_LS_OUT_4 | OUT |
| 26 | EN_LS_OUT_5 | OUT |
| 27 | EN_LS_OUT_6 | OUT |
| 28 | EN_LS_OUT_7 | OUT |
| 29 | Unused | n/a |
| 30 | Unused | n/a |
| 31 | Unused | n/a |
| 32 | DIG_IN_1 | IN |
| 33 | DIG_IN_2 | IN |
| 34 | DIG_IN_3 | IN |
| 35 | DIG_IN_4 | IN |
| 36 | SD_BOOT_JMP# | IN |
| 37 | DIO_IN_1 | IN |
| 38 | DIO_IN_2 | IN |
| 39 | DIO_IN_3 | IN |
| 40 | DIO_IN_4 | IN |
| 41 | DIO_IN_5 | IN |
| 42 | DIO_IN_6 | IN |
| 43 | DIO_IN_7 | IN |