TS-7180 FPGA: Difference between revisions
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The TS-7180 FPGA | The recommended way to access the TS-7180 FPGA's forty-four GPIO registers is with Linux's <code>gpioset</code> and <code>gpioget</code> commands (see: [[TS-7180 DIO|GPIO]]). | ||
The | The supplied <code>tshwctl</code> utility may also be used to access these registers; run <code>tshwctl -h</code> to see how to use it. | ||
The tables below | Internally, the TS-7180 accesses its FPGA registers over the 6UL's I2C bus 3. You should only need to do this in programming environments that lack both of those methods mentioned above. The FPGA is available at I2C addresses 0x28-0x2f. First write the address (which is '''two''' bytes wide), followed by the data, which is one byte. | ||
The tables below lists all FPGA registers and their functions. | |||
{| class="wikitable" | {| class="wikitable" | ||
Line 12: | Line 14: | ||
! Description | ! Description | ||
|- | |- | ||
| rowspan=4 | 0-43 | | rowspan=4 | 0-43<ref>Each address value corresponds to one GPIO number (n) [[#FPGA GPIOs|in the table below]].</ref> | ||
| 7:3 | | 7:3 | ||
| Reserved (Write 0) | | Reserved (Write 0) | ||
Line 25: | Line 27: | ||
| GPIOn Output Enable | | GPIOn Output Enable | ||
|- | |- | ||
| rowspan= | | rowspan=2 | 307 | ||
| 0 | | 7:3 | ||
| BT/ | | Reserved (Write 0) | ||
|- | |||
| 2:0 | |||
| XBee/Nimbelink/MultiTech Cell-modem UART selector (default: 0) | |||
{| class=wikitable | |||
! Value | |||
! Function | |||
|- | |||
| 0 | |||
| Leave disconnected | |||
|- | |||
| 1 | |||
| Steal UART3 (ttymxc2) from BT | |||
|- | |||
| 2 | |||
| Steal UART4 (ttymxc3) from RS-485 | |||
|- | |||
| 3 | |||
| Steal UART6 (ttymxc5) from RS-232 (on P5 pins 10/11) | |||
|- | |||
| 4 | |||
| Steal UART7 (ttymxc6) from RS-232 (on P5 pins 7/8) | |||
|- | |||
| 5 | |||
| Steal UART8 (ttymxc7) from GPS | |||
|} | |||
|- | |||
| rowspan=2 | 308 | |||
| 7:3 | |||
| Reserved (Write 0) | |||
|- | |||
| 2:0 | |||
| HD12 UART selector (default: 0) | |||
{| class=wikitable | |||
! Value | |||
! Function | |||
|- | |||
| 0 | |||
| Leave disconnected | |||
|- | |||
| 1 | |||
| Steal UART3 (ttymxc2) from BT | |||
|- | |||
| 2 | |||
| Steal UART4 (ttymxc3) from RS-485 | |||
|- | |||
| 3 | |||
| Steal UART6 (ttymxc5) from RS-232 (on P5 pins 10/11) | |||
|- | |||
| 4 | |||
| Steal UART7 (ttymxc6) from RS-232 (on P5 pins 7/8) | |||
|- | |- | ||
| | | 5 | ||
| | | Steal UART8 (ttymxc7) from GPS | ||
|} | |||
|- | |- | ||
| rowspan=1 | 309 | | rowspan=1 | 309 | ||
| 0 | | 0 | ||
| PWM control<ref>Write 1 to this address to route the | | PWM control<ref>Write 1 to this address to route the CPU PWM to <code>DIO_1</code></ref> | ||
|- | |||
|310 | |||
| 7:0 | |||
| GPIO chip 0/pin 18 (<code>SPARE_1</code>) MUX<ref name="FPGA_16">Requires a board with [[#FPGA_Revisions|FPGA version 16]] or later.</ref> <br>(1 = connected, 0 = ignored) | |||
{| class=wikitable | |||
! Bit | |||
! Enable | |||
|- | |||
| 0 | |||
| DIG_IN_1 | |||
|- | |||
| 1 | |||
| DIG_IN_2 | |||
|- | |||
| 2 | |||
| DIG_IN_3 | |||
|- | |||
| 3 | |||
| DIG_IN_4 | |||
|- | |||
| 4 | |||
| DIO_1_IN | |||
|- | |||
| 5 | |||
| DIO_2_IN | |||
|- | |||
| 6 | |||
| DIO_3_IN | |||
|- | |||
| 7 | |||
| DIO_4_IN | |||
|- | |||
|} | |||
|- | |||
| 311 | |||
| 7:0 | |||
| Polarity into GPIO chip 0/pin 18 (<code>SPARE_1</code>) MUX<ref name="FPGA_16"/> | |||
{| class=wikitable | |||
! Bit | |||
! Active High EN | |||
|- | |||
| 0 | |||
| DIG_IN_1 | |||
|- | |||
| 1 | |||
| DIG_IN_2 | |||
|- | |||
| 2 | |||
| DIG_IN_3 | |||
|- | |||
| 3 | |||
| DIG_IN_4 | |||
|- | |||
| 4 | |||
| DIO_1_IN | |||
|- | |||
| 5 | |||
| DIO_2_IN | |||
|- | |||
| 6 | |||
| DIO_3_IN | |||
|- | |||
| 7 | |||
| DIO_4_IN | |||
|- | |||
|} | |||
|- | |- | ||
|} | |} | ||
<References /> | <References /> | ||
== FPGA GPIOs == | |||
The FPGA's GPIOs are "gpiochip5" in the Linux GPIO subsystem. | |||
{| class="wikitable sortable" | {| class="wikitable sortable" | ||
|+ FPGA GPIO | |+ FPGA GPIO | ||
Line 165: | Line 286: | ||
|- | |- | ||
| 29 | | 29 | ||
| | | MT_RESET# <ref>Requires a board with [[#FPGA_Revisions|FPGA version 16]] or later.</ref> | ||
| | | OUT | ||
|- | |- | ||
| 30 | | 30 | ||
Line 225: | Line 346: | ||
|- | |- | ||
|} | |} | ||
<References /> | <References /> |
Latest revision as of 11:10, 11 May 2023
The recommended way to access the TS-7180 FPGA's forty-four GPIO registers is with Linux's gpioset
and gpioget
commands (see: GPIO).
The supplied tshwctl
utility may also be used to access these registers; run tshwctl -h
to see how to use it.
Internally, the TS-7180 accesses its FPGA registers over the 6UL's I2C bus 3. You should only need to do this in programming environments that lack both of those methods mentioned above. The FPGA is available at I2C addresses 0x28-0x2f. First write the address (which is two bytes wide), followed by the data, which is one byte.
The tables below lists all FPGA registers and their functions.
Address | Bits | Description | ||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0-43[1] | 7:3 | Reserved (Write 0) | ||||||||||||||||||
2 | GPIOn Input Data | |||||||||||||||||||
1 | GPIOn Output Data | |||||||||||||||||||
0 | GPIOn Output Enable | |||||||||||||||||||
307 | 7:3 | Reserved (Write 0) | ||||||||||||||||||
2:0 | XBee/Nimbelink/MultiTech Cell-modem UART selector (default: 0)
| |||||||||||||||||||
308 | 7:3 | Reserved (Write 0) | ||||||||||||||||||
2:0 | HD12 UART selector (default: 0)
| |||||||||||||||||||
309 | 0 | PWM control[2] | ||||||||||||||||||
310 | 7:0 | GPIO chip 0/pin 18 (SPARE_1 ) MUX[3] (1 = connected, 0 = ignored)
| ||||||||||||||||||
311 | 7:0 | Polarity into GPIO chip 0/pin 18 (SPARE_1 ) MUX[3]
|
- ↑ Each address value corresponds to one GPIO number (n) in the table below.
- ↑ Write 1 to this address to route the CPU PWM to
DIO_1
- ↑ 3.0 3.1 Requires a board with FPGA version 16 or later.
FPGA GPIOs
The FPGA's GPIOs are "gpiochip5" in the Linux GPIO subsystem.
IO Number | Pad | Direction |
---|---|---|
0 | WIFI_RESET# | OUT |
1 | EN_WIFI_PWR | OUT |
2 | EN_YEL_LED# | OUT |
3 | EN_GREEN_LED# | OUT |
4 | EN_RED_LED# | OUT |
5 | EN_BLUE_LED# | OUT |
6 | EN_CL_1 | OUT |
7 | EN_CL_2 | OUT |
8 | EN_CL_3 | OUT |
9 | EN_CL_4 | OUT |
10 | EN_ADC1_10V | OUT |
11 | EN_ADC2_10V | OUT |
12 | EN_ADC3_10V | OUT |
13 | EN_ADC4_10V | OUT |
14 | EN_SD_POWER | OUT |
15 | EN_USB_HOST_5V | OUT |
16 | EN_OFF_BD_5V | OUT |
17 | EN_CELL_MODEM_PWR | OUT |
18 | EN_NIMBEL_3.3V | OUT |
19 | EN_GPS_PWR# | OUT |
20 | EN_CAN_XVR# | OUT |
21 | EN_232_XVR | OUT |
22 | EN_LS_OUT_1 | OUT |
23 | EN_LS_OUT_2 | OUT |
24 | EN_LS_OUT_3 | OUT |
25 | EN_LS_OUT_4 | OUT |
26 | EN_LS_OUT_5 | OUT |
27 | EN_LS_OUT_6 | OUT |
28 | EN_LS_OUT_7 | OUT |
29 | MT_RESET# [1] | OUT |
30 | Unused | n/a |
31 | Unused | n/a |
32 | DIG_IN_1 | IN |
33 | DIG_IN_2 | IN |
34 | DIG_IN_3 | IN |
35 | DIG_IN_4 | IN |
36 | SD_BOOT_JMP# | IN |
37 | DIO_IN_1 | IN |
38 | DIO_IN_2 | IN |
39 | DIO_IN_3 | IN |
40 | DIO_IN_4 | IN |
41 | DIO_IN_5 | IN |
42 | DIO_IN_6 | IN |
43 | DIO_IN_7 | IN |
- ↑ Requires a board with FPGA version 16 or later.