TS-7180 FPGA
From embeddedTS Manuals
The recommended way to access the TS-7180 FPGA's forty-four GPIO registers is with Linux's gpioset
and gpioget
commands (see: GPIO).
The supplied tshwctl
utility may also be used to access these registers; run tshwctl -h
to see how to use it.
Internally, the TS-7180 accesses its FPGA registers over the 6UL's I2C bus 3. You should only need to do this in programming environments that lack both of those methods mentioned above. The FPGA is available at I2C addresses 0x28-0x2f. First write the address (which is two bytes wide), followed by the data, which is one byte.
The tables below lists all FPGA registers and their functions.
Address | Bits | Description | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0-43[1] | 7:3 | Reserved (Write 0) | |||||||||||||
2 | GPIOn Input Data | ||||||||||||||
1 | GPIOn Output Data | ||||||||||||||
0 | GPIOn Output Enable | ||||||||||||||
307 | 7:3 | Reserved (Write 0) | |||||||||||||
2:0 | XBee/Nimbelink/MultiTech Cell-modem UART selector (default: 0)
| ||||||||||||||
308 | 7:3 | Reserved (Write 0) | |||||||||||||
2:0 | HD1 UART selector (default: 0)
| ||||||||||||||
309 | 0 | PWM control[2] |
- ↑ Each address value corresponds to one GPIO number (n) in the table below.
- ↑ Write 1 to this address to route the cpu PWM to DIO_1
FPGA GPIOs
The FPGA's GPIOs are "gpiochip5" in the Linux GPIO subsystem.
IO Number | Pad | Direction |
---|---|---|
0 | WIFI_RESET# | OUT |
1 | EN_WIFI_PWR | OUT |
2 | EN_YEL_LED# | OUT |
3 | EN_GREEN_LED# | OUT |
4 | EN_RED_LED# | OUT |
5 | EN_BLUE_LED# | OUT |
6 | EN_CL_1 | OUT |
7 | EN_CL_2 | OUT |
8 | EN_CL_3 | OUT |
9 | EN_CL_4 | OUT |
10 | EN_ADC1_10V | OUT |
11 | EN_ADC2_10V | OUT |
12 | EN_ADC3_10V | OUT |
13 | EN_ADC4_10V | OUT |
14 | EN_SD_POWER | OUT |
15 | EN_USB_HOST_5V | OUT |
16 | EN_OFF_BD_5V | OUT |
17 | EN_CELL_MODEM_PWR | OUT |
18 | EN_NIMBEL_3.3V | OUT |
19 | EN_GPS_PWR# | OUT |
20 | EN_CAN_XVR# | OUT |
21 | EN_232_XVR | OUT |
22 | EN_LS_OUT_1 | OUT |
23 | EN_LS_OUT_2 | OUT |
24 | EN_LS_OUT_3 | OUT |
25 | EN_LS_OUT_4 | OUT |
26 | EN_LS_OUT_5 | OUT |
27 | EN_LS_OUT_6 | OUT |
28 | EN_LS_OUT_7 | OUT |
29 | MT_RESET# [1] | OUT |
30 | Unused | n/a |
31 | Unused | n/a |
32 | DIG_IN_1 | IN |
33 | DIG_IN_2 | IN |
34 | DIG_IN_3 | IN |
35 | DIG_IN_4 | IN |
36 | SD_BOOT_JMP# | IN |
37 | DIO_IN_1 | IN |
38 | DIO_IN_2 | IN |
39 | DIO_IN_3 | IN |
40 | DIO_IN_4 | IN |
41 | DIO_IN_5 | IN |
42 | DIO_IN_6 | IN |
43 | DIO_IN_7 | IN |
- ↑ Requires a board with FPGA version 16 or later.