TS-7250-V3 ADC Header: Difference between revisions

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| 1
| 1
| ii0:device0/voltage0
| iio:device0/voltage0
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| 2
| 2
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| 3
| 3
| ii0:device0/voltage1
| iio:device0/voltage1
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| 4
| 4
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| 5
| 5
| ii0:device0/voltage5
| iio:device0/voltage5
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| 6
| 6
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| 7
| 7
| ii0:device0/voltage8
| iio:device0/voltage8
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| 8
| 8
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| 9
| 9
| ii0:device0/voltage9
| iio:device0/voltage9
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| 10
| 10

Revision as of 15:19, 6 July 2021

The ADC header supports 5 channels of 0-30VDC ADC. Of these 5, 3 channels support sampling 0-20mA current loops. These channels are sampled from /sys/devices/platform/soc/2100000.aips-bus/2198000.adc/iio:device0#/. See the ADC section for more details on sampling these pins.

Signals Pin Layout
Pin Signal
1 iio:device0/voltage0
2 GND
3 iio:device0/voltage1
4 GND
5 iio:device0/voltage5
6 GND
7 iio:device0/voltage8
8 GND
9 iio:device0/voltage9
10 GND

TS-7250-V3-ADC.svg

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